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FPGA: Use 200 Hz for 100 Gbit/s design

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leonarski_f
2023-08-15 17:31:05 +02:00
parent f66fc95ecc
commit 2a0e4b7d4a
1 changed files with 9 additions and 11 deletions
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20
fpga/scripts/bd_pcie_100g.tcl
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@@ -308,20 +308,18 @@ proc create_root_design { parentCell } {
# Create instance: clk_wiz_0, and set properties
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
set_property -dict [ list \
CONFIG.CLKOUT1_JITTER {151.636} \
CONFIG.CLKOUT1_PHASE_ERROR {98.575} \
CONFIG.CLKOUT1_JITTER {132.683} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
CONFIG.CLKOUT2_JITTER {130.958} \
CONFIG.CLKOUT2_PHASE_ERROR {98.575} \
CONFIG.CLKOUT2_JITTER {115.831} \
CONFIG.CLKOUT2_PHASE_ERROR {87.180} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_JITTER {110.209} \
CONFIG.CLKOUT3_PHASE_ERROR {98.575} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {250.000} \
CONFIG.CLKOUT3_JITTER {102.086} \
CONFIG.CLKOUT3_PHASE_ERROR {87.180} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} \
CONFIG.CLKOUT3_USED {true} \
CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {10} \
CONFIG.MMCM_CLKOUT2_DIVIDE {4} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {12} \
CONFIG.MMCM_CLKOUT2_DIVIDE {6} \
CONFIG.NUM_OUT_CLKS {3} \
CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
CONFIG.RESET_PORT {reset} \