FPGA: Use 250 Hz for 100 Gbit/s design + adjust TCL scripts

.gitlab-ci.yml

@@ -186,7 +186,7 @@ test:x86:xia2.ssx:
     - xia2.ssx image=writing_test_master.h5 space_group=P43212 unit_cell=78.551,78.551,36.914,90.000,90.000,90.000
 
 
-synthesis:vivado_pcie:
+synthesis:vivado_pcie_200g:
   stage: synthesis
   variables:
     GIT_SUBMODULE_STRATEGY: recursive
@@ -216,3 +216,34 @@ synthesis:vivado_pcie:
     - cmake3 ..
     - make action_pcie
   needs: ["build:x86:gcc", "build:x86:vitis_hls", "test:x86:gcc"]
+
+synthesis:vivado_pcie_100g:
+  stage: synthesis
+  variables:
+    GIT_SUBMODULE_STRATEGY: recursive
+    CC: gcc
+    CXX: g++
+  allow_failure: true
+  rules:
+    - if: '$CI_PIPELINE_SOURCE == "push"'
+      changes:
+        - fpga/hls/*
+        - fpga/hdl/*
+        - fpga/scripts/*
+        - fpga/xdc/*
+        - common/Definitions.h
+  tags:
+    - vivado
+  artifacts:
+    paths:
+      - build/fpga/*.mcs
+      - build/fpga/*.bit
+    expire_in: 1 week
+  script:
+    - source /opt/grpc/grpc.sh
+    - source /opt/Xilinx/Vivado/2022.1/settings64.sh
+    - mkdir -p build
+    - cd build
+    - cmake3 ..
+    - make action_pcie_100g
+  needs: ["build:x86:gcc", "build:x86:vitis_hls", "test:x86:gcc"]

fpga/CMakeLists.txt

@@ -25,11 +25,11 @@ IF(VIVADO_HLS AND VIVADO)
 
     ADD_CUSTOM_TARGET(action_pcie DEPENDS action/hw/hdl/action_config.v hls
             COMMAND ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_SOURCE_DIR}/scripts/build_pcie_design.tcl
-            COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
+            COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie_200gbit VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
             )
 
-    ADD_CUSTOM_TARGET(action_pcie_1stream DEPENDS action/hw/hdl/action_config.v hls
-            COMMAND ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_SOURCE_DIR}/scripts/build_pcie_design_1stream.tcl
-            COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
+    ADD_CUSTOM_TARGET(action_pcie_100g DEPENDS action/hw/hdl/action_config.v hls
+            COMMAND ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_SOURCE_DIR}/scripts/build_pcie_design_100g.tcl
+            COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie_100gbit VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
     )
 ENDIF()

fpga/scripts/bd_pcie_100g.tcl

@@ -308,18 +308,20 @@ proc create_root_design { parentCell } {
   # Create instance: clk_wiz_0, and set properties
   set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
   set_property -dict [ list \
-   CONFIG.CLKOUT1_JITTER {132.683} \
+   CONFIG.CLKOUT1_JITTER {151.636} \
+   CONFIG.CLKOUT1_PHASE_ERROR {98.575} \
    CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
-   CONFIG.CLKOUT2_JITTER {115.831} \
-   CONFIG.CLKOUT2_PHASE_ERROR {87.180} \
+   CONFIG.CLKOUT2_JITTER {130.958} \
+   CONFIG.CLKOUT2_PHASE_ERROR {98.575} \
    CONFIG.CLKOUT2_USED {true} \
-   CONFIG.CLKOUT3_JITTER {102.086} \
-   CONFIG.CLKOUT3_PHASE_ERROR {87.180} \
-   CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} \
+   CONFIG.CLKOUT3_JITTER {110.209} \
+   CONFIG.CLKOUT3_PHASE_ERROR {98.575} \
+   CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {250.000} \
    CONFIG.CLKOUT3_USED {true} \
-   CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \
-   CONFIG.MMCM_CLKOUT1_DIVIDE {12} \
-   CONFIG.MMCM_CLKOUT2_DIVIDE {6} \
+   CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \
+   CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} \
+   CONFIG.MMCM_CLKOUT1_DIVIDE {10} \
+   CONFIG.MMCM_CLKOUT2_DIVIDE {4} \
    CONFIG.NUM_OUT_CLKS {3} \
    CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
    CONFIG.RESET_PORT {reset} \

fpga/scripts/build_pcie_design_100g.tcl

@@ -50,7 +50,7 @@ source $origin_dir/hbm_u55c.tcl
 source $origin_dir/jfjoch.tcl
 source $origin_dir/pcie_dma.tcl
 source $origin_dir/mac_100g_pcie.tcl
-source $origin_dir/bd_pcie_1stream.tcl >> build_pcie.log
+source $origin_dir/bd_pcie_100g.tcl >> build_pcie.log
 
 make_wrapper -files [get_files "vivado/jfjoch_pcie.srcs/sources_1/bd/jfjoch_pcie/jfjoch_pcie.bd"] -top >> make_wrapper.log
 add_files -norecurse "vivado/jfjoch_pcie.gen/sources_1/bd/jfjoch_pcie/hdl/jfjoch_pcie_wrapper.v"