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FPGA: load calibration works as dedicated function of the card

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This commit is contained in:
leonarski_f
2023-09-12 14:34:42 +02:00
parent 7a635f1ee8
commit 9d01630cfc
17 changed files with 177 additions and 171 deletions
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6
fpga/hls/hls_jfjoch.h
View File

@@ -101,9 +101,11 @@ void data_collection_fsm(AXI_STREAM &eth_in,
ap_uint<4> nstorage_cells,
ap_uint<32> hbm_size_bytes);
void load_calibration(STREAM_512 &data_in, STREAM_512 &data_out,
ap_uint<256> *d_hbm_p0,
void load_calibration(ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<8> modules,
ap_uint<5> storage_cells,
ap_uint<32> hbm_size_bytes,
hls::stream<axis_datamover_ctrl> &datamover_in_cmd,
hls::stream<ap_axiu<512,1,1,1> > &host_memory_in,
uint64_t in_mem_location[LOAD_CALIBRATION_BRAM_SIZE]);

97
fpga/hls/load_calibration.cpp
View File

@@ -9,79 +9,68 @@
// * gain factors for module m at location: 2 + gain level * NMODULES + m
// * pedestal factors for module m and storage cell s at location: 2 + 3 * NMODULES + (gain level * 16 + s ) * NMODULES + m
void load_calibration(STREAM_512 &data_in, STREAM_512 &data_out,
ap_uint<256> *d_hbm_p0,
void load_calibration(ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<8> modules,
ap_uint<5> storage_cells,
ap_uint<32> hbm_size_bytes,
hls::stream<axis_datamover_ctrl> &datamover_in_cmd,
hls::stream<ap_axiu<512,1,1,1> > &host_memory_in,
uint64_t in_mem_location[LOAD_CALIBRATION_BRAM_SIZE]) {
#pragma HLS INTERFACE ap_ctrl_none port=return
uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) {
#pragma HLS INTERFACE mode=s_axilite port=return
#pragma HLS INTERFACE mode=s_axilite port=in_mem_location
#pragma HLS INTERFACE register both axis port=datamover_in_cmd
#pragma HLS INTERFACE register both axis port=host_memory_in
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=data_out
#pragma HLS INTERFACE bram port=in_mem_location storage_type=rom_1p
#pragma HLS INTERFACE mode=s_axilite port=modules
#pragma HLS INTERFACE mode=s_axilite port=storage_cells
#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
#pragma HLS INTERFACE m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
#pragma HLS INTERFACE m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
packet_512_t packet_in;
if (storage_cells > 16)
return;
if (modules > MAX_MODULES_FPGA)
return;
data_in >> packet_in;
ap_uint<5> modules = ACT_REG_NMODULES(packet_in.data);
ap_uint<5> storage_cells = ACT_REG_NSTORAGE_CELLS(packet_in.data);
ap_uint<1> conversion = (ACT_REG_MODE(packet_in.data) & MODE_CONV) ? 1 : 0;
ap_uint<32> hbm_size_256b = ACT_REG_HBM_SIZE_256b(packet_in.data);
if (conversion) {
ap_uint<16> addr = 0;
for (int c = 0; c < 3; c++) {
size_t offset_hbm_0 = (2 * c) * hbm_size_256b;
size_t offset_hbm_1 = (2 * c + 1) * hbm_size_256b;
read_gain:
for (int i = 0; i < modules * RAW_MODULE_SIZE * sizeof(int16_t) / 64; i++) {
ap_uint<16> addr = 0;
for (int c = 0; c < 3; c++) {
size_t offset_hbm_0 = (2 * c) * hbm_size_bytes / 32;
size_t offset_hbm_1 = (2 * c + 1) * hbm_size_bytes / 32;
read_gain:
for (int i = 0; i < modules * RAW_MODULE_SIZE * sizeof(int16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
if (i % (RAW_MODULE_SIZE * sizeof(uint16_t) / 64) == 0) {
setup_datamover(datamover_in_cmd, in_mem_location[addr], RAW_MODULE_SIZE * sizeof(int16_t));
addr++;
}
ap_axiu<512, 1, 1, 1> data_packet;
host_memory_in >> data_packet;
d_hbm_p0[offset_hbm_0 + i] = data_packet.data(255, 0);
d_hbm_p1[offset_hbm_1 + i] = data_packet.data(511, 256);
if (i % (RAW_MODULE_SIZE * sizeof(uint16_t) / 64) == 0) {
setup_datamover(datamover_in_cmd, in_mem_location[addr], RAW_MODULE_SIZE * sizeof(int16_t));
addr++;
}
}
ap_axiu<512, 1, 1, 1> data_packet;
host_memory_in >> data_packet;
read_pedestal:
for (int c = 0; c < 3; c++) {
size_t offset_hbm_0 = (6 + 2 * c) * hbm_size_256b;
size_t offset_hbm_1 = (6 + 2 * c + 1) * hbm_size_256b;
for (int i = 0; i < storage_cells * modules * RAW_MODULE_SIZE * sizeof(int16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
if (i % (RAW_MODULE_SIZE * sizeof(uint16_t) / 64) == 0) {
setup_datamover(datamover_in_cmd, in_mem_location[addr], RAW_MODULE_SIZE * sizeof(int16_t));
addr++;
}
ap_axiu<512, 1, 1, 1> data_packet;
host_memory_in >> data_packet;
d_hbm_p0[offset_hbm_0 + i] = data_packet.data(255, 0);
d_hbm_p1[offset_hbm_1 + i] = data_packet.data(511, 256);
}
d_hbm_p0[offset_hbm_0 | i] = data_packet.data(255, 0);
d_hbm_p1[offset_hbm_1 | i] = data_packet.data(511, 256);
}
}
data_out << packet_in;
read_pedestal:
for (int c = 0; c < 3; c++) {
size_t offset_hbm_0 = (6 + 2 * c) * hbm_size_bytes / 32;
size_t offset_hbm_1 = (6 + 2 * c + 1) * hbm_size_bytes / 32;
data_in >> packet_in;
while (!packet_in.user) {
for (int i = 0; i < modules * storage_cells * RAW_MODULE_SIZE * sizeof(int16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
data_out << packet_in;
data_in >> packet_in;
if (i % (RAW_MODULE_SIZE * sizeof(uint16_t) / 64) == 0) {
setup_datamover(datamover_in_cmd, in_mem_location[addr], RAW_MODULE_SIZE * sizeof(int16_t));
addr++;
}
ap_axiu<512, 1, 1, 1> data_packet;
host_memory_in >> data_packet;
d_hbm_p0[offset_hbm_0 | i] = data_packet.data(255, 0);
d_hbm_p1[offset_hbm_1 | i] = data_packet.data(511, 256);
}
}
data_out << packet_in;
}

5
fpga/pcie_driver/jfjoch_drv.c
View File

@@ -82,10 +82,6 @@ static int jfjoch_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id
drvdata->git_sha1 = status.git_sha1;
drvdata->max_modules = status.max_modules;
err = jfjoch_setup_calibration(pdev);
if (err)
goto deregister_misc;
jfjoch_setup_cms(drvdata);
jfjoch_setup_network(drvdata);
@@ -114,7 +110,6 @@ void jfjoch_reset(struct jfjoch_drvdata *drvdata) {
pci_reset_function(drvdata->pdev);
jfjoch_setup_cms(drvdata);
jfjoch_setup_calibration(drvdata->pdev);
dev_info(drvdata->miscdev.this_device, "Jungfraujoch FPGA restarted");
}

10
fpga/pcie_driver/jfjoch_drv.h
View File

@@ -37,12 +37,18 @@
// Offset for BAR #0 for action configuration
#define ACTION_CONFIG_OFFSET (0x010000)
#define MAILBOX_OFFSET (0x030000)
#define CALIB_BRAM_OFFSET (0x060000)
#define LOAD_CALIBRATION_OFFSET (0x060000)
#define CMS_OFFSET (0x0C0000)
#define CMAC_OFFSET (0x020000)
#define PCIE_OFFSET (0x090000)
#define INT_PKT_GEN_OFFSET (0x100000)
#define ADDR_LOAD_CALIBRATION_CTRL (0x000000)
#define ADDR_LOAD_CALIBRATION_MOD (0x000010)
#define ADDR_LOAD_CALIBRATION_SC (0x000018)
#define ADDR_LOAD_CALIBRATION_MEM (0x002000)
#define ADDR_CMS_CONTROL_REG 0x028018
#define ADDR_CMS_MB_RESETN_REG 0x020000
#define ADDR_CMS_FPGA_TEMP_INS_REG 0x028100 // in C
@@ -86,7 +92,6 @@ int jfjoch_cdev_mmap(struct file *file, struct vm_area_struct *vma);
int jfjoch_cdev_release(struct inode *inode, struct file *file);
int jfjoch_cdev_open(struct inode *inode, struct file *file);
int jfjoch_setup_calibration(struct pci_dev *pdev);
void jfjoch_setup_cms(struct jfjoch_drvdata *drvdata);
void jfjoch_setup_network(struct jfjoch_drvdata *drvdata);
@@ -105,6 +110,7 @@ void jfjoch_set_ipv4_addr(struct jfjoch_drvdata *drvdata, const u32 *addr);
void jfjoch_get_ipv4_addr(struct jfjoch_drvdata *drvdata, u32 *addr);
void jfjoch_load_int_pkt_gen(struct jfjoch_drvdata *drvdata, char* output);
void jfjoch_save_int_pkt_gen(struct jfjoch_drvdata *drvdata, const char* input);
int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig *config);
u64 jfjoch_read_mac_addr(struct jfjoch_drvdata *drvdata);

36
fpga/pcie_driver/jfjoch_function.c
View File

@@ -294,4 +294,40 @@ void jfjoch_get_env_data(struct jfjoch_drvdata *drvdata, struct ActionEnvParams
void jfjoch_clr_net_counters(struct jfjoch_drvdata *drvdata) {
iowrite32(1 << 3, drvdata->bar0 + ACTION_CONFIG_OFFSET);
iowrite32(0, drvdata->bar0 + ACTION_CONFIG_OFFSET);
}
int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig *config) {
struct device *const dev = &drvdata->pdev->dev;
u32 i;
u32 cell_count = config->nmodules * (3 + 3 * config->nstorage_cells);
if (cell_count > drvdata->nbuf) {
dev_err(dev, "Not enough buffers to support this card\n");
return -EINVAL;
}
for (i = 0; i < cell_count; i++) {
u64 addr = drvdata->bufs[i].dma_address;
iowrite32(PCI_DMA_L(addr), drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_MEM + i * 2 * 4);
iowrite32(PCI_DMA_H(addr), drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_MEM + (i * 2 + 1) * 4);
}
iowrite32(config->nmodules, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_MOD);
iowrite32(config->nstorage_cells, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_SC);
iowrite32(0x1, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_CTRL);
i = 0;
while (i < 1000) {
if (ioread32(drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_CTRL) & (1 << 1))
break;
msleep(10);
i++;
}
if (i == 1000) {
dev_err(dev, "Load calibration didn't finish in 10 seconds\n");
return -ETIMEDOUT;
}
return 0;
}

4
fpga/pcie_driver/jfjoch_ioctl.c
View File

@@ -38,6 +38,10 @@ long jfjoch_cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) {
return -EFAULT;
jfjoch_set_config(drvdata, &config);
return 0;
case IOCTL_JFJOCH_LOAD_CALIB:
if (copy_from_user(&config, (char *) arg, sizeof(struct ActionConfig)) != 0)
return -EFAULT;
return jfjoch_load_calibration(drvdata, &config);
case IOCTL_JFJOCH_GET_ENV_DATA:
jfjoch_get_env_data(drvdata, &env_params);
if (copy_to_user((char *) arg, &env_params, sizeof(struct ActionEnvParams)) != 0)

1
fpga/pcie_driver/jfjoch_ioctl.h
View File

@@ -35,5 +35,6 @@
#define IOCTL_JFJOCH_GET_IPV4 _IOR(IOCTL_JFJOCH_MAGIC, 18, uint32_t)
#define IOCTL_JFJOCH_SET_INT_PKT _IOW(IOCTL_JFJOCH_MAGIC, 19, char *)
#define IOCTL_JFJOCH_GET_INT_PKT _IOR(IOCTL_JFJOCH_MAGIC, 20, char *)
#define IOCTL_JFJOCH_LOAD_CALIB _IOW(IOCTL_JFJOCH_MAGIC, 21, struct ActionConfig)
#endif //JUNGFRAUJOCH_JFJOCH_IOCTL_H

19
fpga/pcie_driver/jfjoch_memory.c
View File

@@ -53,25 +53,6 @@ void jfjoch_free_phys_continous_buf(struct pci_dev *pdev) {
kfree(drvdata->bufs);
}
int jfjoch_setup_calibration(struct pci_dev *pdev) {
struct jfjoch_drvdata *drvdata = pci_get_drvdata(pdev);
u32 i;
u32 cell_count = drvdata->max_modules * (3 + 3 * 16) + 1;
if ((cell_count > nbuffer) || (cell_count >= LOAD_CALIBRATION_BRAM_SIZE)) {
dev_err(&pdev->dev, "Not enough buffers to support this card\n");
return -EINVAL;
}
for (i = 0; i < cell_count; i++) {
u64 addr = drvdata->bufs[i].dma_address;
iowrite32(PCI_DMA_L(addr), drvdata->bar0 + CALIB_BRAM_OFFSET + i * 2 * 4);
iowrite32(PCI_DMA_H(addr), drvdata->bar0 + CALIB_BRAM_OFFSET + (i * 2 + 1) * 4);
}
return 0;
}
int jfjoch_cdev_mmap(struct file *file, struct vm_area_struct *vma) {
unsigned long offset, buffer_number, len;

4
fpga/scripts/bd_pcie.tcl
View File

@@ -146,10 +146,10 @@ xilinx.com:ip:hbm:1.0\
xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:axis_data_fifo:2.0\
xilinx.com:ip:axis_register_slice:1.1\
xilinx.com:ip:blk_mem_gen:8.4\
psi.ch:hls:data_collection_fsm:1.0\
psi.ch:hls:host_writer:1.0\
psi.ch:hls:internal_packet_generator:1.0\
xilinx.com:ip:blk_mem_gen:8.4\
psi.ch:hls:jf_conversion:1.0\
psi.ch:hls:load_calibration:1.0\
xilinx.com:ip:mailbox:2.1\
@@ -435,7 +435,7 @@ proc create_root_design { parentCell } {
assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/mailbox_0/S0_AXI/Reg] -force
assign_bd_address -offset 0x00040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] -force
assign_bd_address -offset 0x00050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_calibration_addr/S_AXI/Mem0] -force
assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/load_calibration_0/s_axi_control/Reg] -force
assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force
assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force
assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force

79
fpga/scripts/jfjoch.tcl
View File

@@ -2,9 +2,9 @@
## SPDX-License-Identifier: CERN-OHL-S-2.0
# Hierarchical cell: jungfraujoch
proc create_hier_cell_jungfraujoch { parentCell nameHier } {
proc create_hier_cell_jungfraujoch_0 { parentCell nameHier } {
variable script_folder
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_jungfraujoch_0() - Empty argument(s)!"}
@@ -95,14 +95,6 @@ variable script_folder
CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \
] $action_config_0
# Create instance: axi_bram_ctrl_calibration_addr, and set properties
set axi_bram_ctrl_calibration_addr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_calibration_addr ]
set_property -dict [ list \
CONFIG.PROTOCOL {AXI4LITE} \
CONFIG.READ_LATENCY {1} \
CONFIG.SINGLE_PORT_BRAM {1} \
] $axi_bram_ctrl_calibration_addr
# Create instance: axi_bram_ctrl_internal_packet_generator_0, and set properties
set axi_bram_ctrl_internal_packet_generator_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_internal_packet_generator_0 ]
set_property -dict [ list \
@@ -165,6 +157,8 @@ variable script_folder
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {block} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \
] $axis_data_fifo_2
# Create instance: axis_data_fifo_3, and set properties
@@ -172,25 +166,16 @@ variable script_folder
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {block} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \
] $axis_data_fifo_3
# Create instance: axis_data_fifo_4, and set properties
set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {block} \
] $axis_data_fifo_4
# Create instance: axis_data_fifo_5, and set properties
set axis_data_fifo_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_5 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {32768} \
CONFIG.FIFO_MEMORY_TYPE {ultra} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \
] $axis_data_fifo_5
] $axis_data_fifo_4
# Create instance: axis_data_fifo_c2h_cmd, and set properties
set axis_data_fifo_c2h_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_c2h_cmd ]
@@ -302,20 +287,6 @@ variable script_folder
CONFIG.HAS_PROG_FULL {0} \
] $axis_work_request_fifo_0
# Create instance: calibration_addr_bram, and set properties
set calibration_addr_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 calibration_addr_bram ]
set_property -dict [ list \
CONFIG.Assume_Synchronous_Clk {true} \
CONFIG.Enable_B {Use_ENB_Pin} \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.Port_A_Write_Rate {50} \
CONFIG.Port_B_Clock {100} \
CONFIG.Port_B_Enable_Rate {100} \
CONFIG.Port_B_Write_Rate {50} \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Use_RSTB_Pin {true} \
] $calibration_addr_bram
# Create instance: data_collection_fsm_0, and set properties
set data_collection_fsm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:data_collection_fsm:1.0 data_collection_fsm_0 ]
@@ -386,27 +357,25 @@ variable script_folder
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins network_stack/M00_AXIS]
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins eth_in] [get_bd_intf_pins network_stack/eth_in]
connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_calibration_addr/BRAM_PORTA] [get_bd_intf_pins calibration_addr_bram/BRAM_PORTB]
connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTB]
connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTA]
connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/addr_in]
connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/M_AXIS] [get_bd_intf_pins jf_conversion_0/addr_in]
connect_bd_intf_net -intf_net axis_addr_fifo_2_M_AXIS1 [get_bd_intf_pins axis_addr_fifo_2/M_AXIS] [get_bd_intf_pins host_writer_0/addr_in]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins load_calibration_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins timer_hbm/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS1 [get_bd_intf_pins axis_data_fifo_4/M_AXIS] [get_bd_intf_pins timer_host/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_5_M_AXIS [get_bd_intf_pins axis_data_fifo_5/M_AXIS] [get_bd_intf_pins host_writer_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins timer_hbm/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS1 [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins timer_host/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_5_M_AXIS [get_bd_intf_pins axis_data_fifo_4/M_AXIS] [get_bd_intf_pins host_writer_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_c2h_cmd_M_AXIS [get_bd_intf_pins m_axis_c2h_datamover_cmd] [get_bd_intf_pins axis_data_fifo_c2h_cmd/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_c2h_data_M_AXIS [get_bd_intf_pins m_axis_c2h_data] [get_bd_intf_pins axis_data_fifo_c2h_data/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_h2c_cmd_M_AXIS [get_bd_intf_pins m_axis_h2c_datamover_cmd] [get_bd_intf_pins axis_data_fifo_h2c_cmd/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_h2c_data_M_AXIS [get_bd_intf_pins axis_data_fifo_h2c_data/M_AXIS] [get_bd_intf_pins axis_register_slice_data_in_0/S_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_2/S_AXIS] [get_bd_intf_pins axis_register_slice_addr_1/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS1 [get_bd_intf_pins axis_register_slice_data_in_0/M_AXIS] [get_bd_intf_pins load_calibration_0/host_memory_in]
connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_data_fifo_5/S_AXIS] [get_bd_intf_pins axis_register_slice_data_1/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins axis_register_slice_data_1/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_2_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/S_AXIS] [get_bd_intf_pins axis_register_slice_addr_0/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_data_0_M_AXIS [get_bd_intf_pins axis_data_fifo_2/S_AXIS] [get_bd_intf_pins axis_register_slice_data_0/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_data_0_M_AXIS [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins axis_register_slice_data_0/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_host_mem_M_AXIS [get_bd_intf_pins axis_data_fifo_c2h_data/S_AXIS] [get_bd_intf_pins axis_register_slice_host_mem/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_udp_M_AXIS [get_bd_intf_pins axis_register_slice_udp/M_AXIS] [get_bd_intf_pins data_collection_fsm_0/eth_in]
connect_bd_intf_net -intf_net axis_udp_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_udp_addr_fifo_0/M_AXIS] [get_bd_intf_pins data_collection_fsm_0/addr_in]
@@ -422,7 +391,7 @@ variable script_folder
connect_bd_intf_net -intf_net internal_packet_generator_0_data_out [get_bd_intf_pins axis_register_slice_data_0/S_AXIS] [get_bd_intf_pins internal_packet_generator_0/data_out]
connect_bd_intf_net -intf_net internal_packet_generator_0_m_axi_frame [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/S_AXI] [get_bd_intf_pins internal_packet_generator_0/m_axi_frame]
connect_bd_intf_net -intf_net jf_conversion_0_addr_out [get_bd_intf_pins axis_register_slice_addr_1/S_AXIS] [get_bd_intf_pins jf_conversion_0/addr_out]
connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out]
connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S00_AXI]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p1] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p1]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p2 [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/S00_AXI]
@@ -435,9 +404,7 @@ variable script_folder
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p9 [get_bd_intf_pins m_axi_d_hbm_p9] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p9]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p10 [get_bd_intf_pins m_axi_d_hbm_p10] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p10]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p11 [get_bd_intf_pins m_axi_d_hbm_p11] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p11]
connect_bd_intf_net -intf_net load_calibration_0_data_out [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins load_calibration_0/data_out]
connect_bd_intf_net -intf_net load_calibration_0_datamover_in_cmd [get_bd_intf_pins axis_data_fifo_h2c_cmd/S_AXIS] [get_bd_intf_pins load_calibration_0/datamover_in_cmd]
connect_bd_intf_net -intf_net load_calibration_0_in_mem_location_PORTA [get_bd_intf_pins calibration_addr_bram/BRAM_PORTA] [get_bd_intf_pins load_calibration_0/in_mem_location_PORTA]
connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p0 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S01_AXI]
connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p1 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_2/S01_AXI]
connect_bd_intf_net -intf_net mailbox_0_M1_AXIS [get_bd_intf_pins axis_work_request_fifo_0/S_AXIS] [get_bd_intf_pins mailbox_0/M1_AXIS]
@@ -446,11 +413,11 @@ variable script_folder
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins smartconnect_0/S00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_bram_ctrl_calibration_addr/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins load_calibration_0/s_axi_control] [get_bd_intf_pins smartconnect_0/M02_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
connect_bd_intf_net -intf_net smartconnect_1_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins smartconnect_2/M00_AXI]
connect_bd_intf_net -intf_net timer_hbm_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins timer_hbm/data_out]
connect_bd_intf_net -intf_net timer_hbm_data_out [get_bd_intf_pins axis_data_fifo_2/S_AXIS] [get_bd_intf_pins timer_hbm/data_out]
connect_bd_intf_net -intf_net timer_host_data_out [get_bd_intf_pins axis_register_slice_data_1/S_AXIS] [get_bd_intf_pins timer_host/data_out]
# Create port connections
@@ -461,19 +428,19 @@ variable script_folder
connect_bd_net -net action_config_0_fpga_ipv4_addr [get_bd_pins action_config_0/fpga_ipv4_addr] [get_bd_pins network_stack/fpga_ipv4_addr]
connect_bd_net -net action_config_0_fpga_mac_addr [get_bd_pins action_config_0/fpga_mac_addr] [get_bd_pins network_stack/fpga_mac_addr]
connect_bd_net -net action_config_0_frames_per_trigger [get_bd_pins action_config_0/nframes] [get_bd_pins data_collection_fsm_0/nframes]
connect_bd_net -net action_config_0_hbm_size_bytes [get_bd_pins action_config_0/hbm_size_bytes] [get_bd_pins data_collection_fsm_0/hbm_size_bytes]
connect_bd_net -net action_config_0_hbm_size_bytes [get_bd_pins action_config_0/hbm_size_bytes] [get_bd_pins data_collection_fsm_0/hbm_size_bytes] [get_bd_pins load_calibration_0/hbm_size_bytes]
connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules]
connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells]
connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy]
connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_addr_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_addr_1/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins internal_packet_generator_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins network_stack/axiclk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
connect_bd_net -net axis_addr_fifo_2_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty]
connect_bd_net -net axis_addr_fifo_2_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_1/almost_full]
connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_2/almost_empty]
connect_bd_net -net axis_addr_fifo_4_almost_full [get_bd_pins action_config_0/last_addr_fifo_full] [get_bd_pins axis_addr_fifo_2/almost_full]
connect_bd_net -net axis_data_fifo_10_almost_empty [get_bd_pins action_config_0/last_data_fifo_empty] [get_bd_pins axis_data_fifo_5/almost_empty]
connect_bd_net -net axis_data_fifo_10_almost_full [get_bd_pins action_config_0/last_data_fifo_full] [get_bd_pins axis_data_fifo_5/almost_full]
connect_bd_net -net axis_data_fifo_4_almost_empty [get_bd_pins action_config_0/calib_data_fifo_empty] [get_bd_pins axis_data_fifo_3/almost_empty]
connect_bd_net -net axis_data_fifo_4_almost_full [get_bd_pins action_config_0/calib_data_fifo_full] [get_bd_pins axis_data_fifo_3/almost_full]
connect_bd_net -net axis_data_fifo_10_almost_empty [get_bd_pins action_config_0/last_data_fifo_empty] [get_bd_pins axis_data_fifo_4/almost_empty]
connect_bd_net -net axis_data_fifo_10_almost_full [get_bd_pins action_config_0/last_data_fifo_full] [get_bd_pins axis_data_fifo_4/almost_full]
connect_bd_net -net axis_data_fifo_4_almost_empty [get_bd_pins action_config_0/calib_data_fifo_empty] [get_bd_pins axis_data_fifo_2/almost_empty]
connect_bd_net -net axis_data_fifo_4_almost_full [get_bd_pins action_config_0/calib_data_fifo_full] [get_bd_pins axis_data_fifo_2/almost_full]
connect_bd_net -net axis_data_fifo_c2h_cmd_almost_empty [get_bd_pins action_config_0/host_mem_cmd_fifo_empty] [get_bd_pins axis_data_fifo_c2h_cmd/almost_empty]
connect_bd_net -net axis_data_fifo_c2h_cmd_almost_full [get_bd_pins action_config_0/host_mem_cmd_fifo_full] [get_bd_pins axis_data_fifo_c2h_cmd/almost_full]
connect_bd_net -net axis_data_fifo_c2h_data_almost_empty [get_bd_pins action_config_0/host_mem_data_fifo_empty] [get_bd_pins axis_data_fifo_c2h_data/almost_empty]
@@ -504,8 +471,8 @@ variable script_folder
connect_bd_net -net network_stack_packets_sls_ap_vld [get_bd_pins action_config_0/packets_sls_valid] [get_bd_pins network_stack/packets_sls_ap_vld]
connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp]
connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld]
connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_addr_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_calibration_addr/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_addr_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_addr_1/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins internal_packet_generator_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter]
connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld]
connect_bd_net -net timer_host_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host/counter]

18
receiver/FPGAAcquisitionDevice.cpp
View File

@@ -66,8 +66,9 @@ void FPGAAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &e
"Mismatch regarding storage cell count in calibration and experiment description");
size_t modules = experiment.GetModulesNum(data_stream);
size_t storage_cells = experiment.GetStorageCellNumber();
if (modules * (3 + 3 * experiment.GetStorageCellNumber()) > buffer_device.size())
if (modules * (3 + 3 * storage_cells) > buffer_device.size())
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Not enough host/FPGA buffers to load all calibration constants");
@@ -77,7 +78,7 @@ void FPGAAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &e
calib.GainCalibration(m).ExportG2(buffer_device[m + modules * 2]);
}
for (int s = 0; s < experiment.GetStorageCellNumber(); s++) {
for (int s = 0; s < storage_cells; s++) {
auto mask = calib.CalculateMask(experiment, s);
for (int m = 0; m < modules; m++) {
auto pedestal_g0 = calib.Pedestal(offset + m, 0, s).GetPedestal();
@@ -85,18 +86,19 @@ void FPGAAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &e
auto pedestal_g2 = calib.Pedestal(offset + m, 2, s).GetPedestal();
for (int i = 0; i < RAW_MODULE_SIZE; i++) {
if (experiment.GetApplyPixelMaskInFPGA() && (mask[(offset + m) * RAW_MODULE_SIZE + i] != 0)) {
buffer_device[m + (3 + 0 * experiment.GetStorageCellNumber() + s) * modules][i] = 16384;
buffer_device[m + (3 + 1 * experiment.GetStorageCellNumber() + s) * modules][i] = 16384;
buffer_device[m + (3 + 2 * experiment.GetStorageCellNumber() + s) * modules][i] = 16384;
buffer_device[(3 + 0 * storage_cells + s) * modules + m][i] = 16384;
buffer_device[(3 + 1 * storage_cells + s) * modules + m][i] = 16384;
buffer_device[(3 + 2 * storage_cells + s) * modules + m][i] = 16384;
} else {
buffer_device[m + (3 + 0 * experiment.GetStorageCellNumber() + s) * modules][i] = pedestal_g0[i];
buffer_device[m + (3 + 1 * experiment.GetStorageCellNumber() + s) * modules][i] = pedestal_g1[i];
buffer_device[m + (3 + 2 * experiment.GetStorageCellNumber() + s) * modules][i] = pedestal_g2[i];
buffer_device[(3 + 0 * storage_cells + s) * modules + m][i] = pedestal_g0[i];
buffer_device[(3 + 1 * storage_cells + s) * modules + m][i] = pedestal_g1[i];
buffer_device[(3 + 2 * storage_cells + s) * modules + m][i] = pedestal_g2[i];
}
}
}
}
HW_LoadCalibration(modules, storage_cells);
}

1
receiver/FPGAAcquisitionDevice.h
View File

@@ -28,6 +28,7 @@ class FPGAAcquisitionDevice : public AcquisitionDevice {
volatile bool stop_work_requests = false;
void SendWorkRequestThread();
virtual void HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) = 0;
virtual bool HW_ReadMailbox(uint32_t values[16]) = 0;
virtual bool HW_SendWorkRequest(uint32_t handle) = 0;
void StartSendingWorkRequests() override;

52
receiver/HLSSimulatedDevice.cpp
View File

@@ -40,13 +40,6 @@ HLSSimulatedDevice::HLSSimulatedDevice(uint16_t data_stream, size_t in_frame_buf
MapBuffersStandard(in_frame_buffer_size_modules,
(3 + 3 * 16) * max_modules + 2, numa_node);
auto in_mem_location32 = (uint32_t *) calibration_addr_bram;
for (int i = 0; i < max_modules * (3 + 3 * 16) + 2; i++) {
in_mem_location32[2 * i ] = ((uint64_t) buffer_device[i]) & UINT32_MAX;
in_mem_location32[2 * i + 1] = ((uint64_t) buffer_device[i]) >> 32;
}
}
void HLSSimulatedDevice::CreateFinalPacket(const DiffractionExperiment& experiment) {
@@ -206,7 +199,6 @@ void HLSSimulatedDevice::HLSMainThread() {
STREAM_512 raw1;
STREAM_512 raw2;
STREAM_512 raw3;
STREAM_512 raw4;
STREAM_512 converted_1;
STREAM_512 converted_2;
@@ -276,24 +268,16 @@ void HLSSimulatedDevice::HLSMainThread() {
}
});
// Load external calibration
hls_cores.emplace_back([&] { load_calibration(raw1, raw2,
hbm.data(),
hbm.data(),
datamover_in.GetCtrlStream(),
datamover_in.GetDataStream(),
calibration_addr_bram); });
// Generate internal packets
hls_cores.emplace_back([&] { internal_packet_generator(raw2, raw3, addr1, addr2,
hls_cores.emplace_back([&] { internal_packet_generator(raw1, raw2, addr1, addr2,
reinterpret_cast<ap_uint<512> *>(internal_pkt_gen_frame.data()),
cancel_data_collection); });
// Timer procedure - count how many times pedestal_corr/gain_corr is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { timer_host(raw3, raw4, counter_hbm); });
hls_cores.emplace_back([&] { timer_host(raw2, raw3, counter_hbm); });
// 2. Apply pedestal & gain corrections
hls_cores.emplace_back([&] { jf_conversion(raw4, converted_1,
hls_cores.emplace_back([&] { jf_conversion(raw3, converted_1,
addr2, addr3,
hbm.data(),
hbm.data(),
@@ -341,9 +325,6 @@ void HLSSimulatedDevice::HLSMainThread() {
if (!raw3.empty())
throw std::runtime_error("Raw3 queue not empty");
if (!raw4.empty())
throw std::runtime_error("Raw4 queue not empty");
if (!converted_1.empty())
throw std::runtime_error("Converted_1 queue not empty");
@@ -370,3 +351,30 @@ void HLSSimulatedDevice::HW_GetStatus(ActionStatus *status) const {
status->max_modules = max_modules;
status->hbm_size_bytes = hbm_if_size;
}
void HLSSimulatedDevice::HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) {
if (logger)
logger->Info("Load calibration start");
auto in_mem_location32 = (uint32_t *) calibration_addr_bram;
for (int i = 0; i < modules * (3 + 3 * storage_cells); i++) {
in_mem_location32[2 * i ] = ((uint64_t) buffer_device[i]) & UINT32_MAX;
in_mem_location32[2 * i + 1] = ((uint64_t) buffer_device[i]) >> 32;
}
load_calibration(hbm.data(),
hbm.data(),
modules,
storage_cells,
hbm_if_size,
datamover_in.GetCtrlStream(),
datamover_in.GetDataStream(),
calibration_addr_bram);
if (logger)
logger->Info("Load calibration done");
if (!datamover_in.GetDataStream().empty())
throw std::runtime_error("Datamover queue is not empty");
}

1
receiver/HLSSimulatedDevice.h
View File

@@ -46,6 +46,7 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice {
bool HW_IsIdle() const override;
bool HW_ReadMailbox(uint32_t values[16]);
bool HW_SendWorkRequest(uint32_t handle) override;
void HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) override;
void HW_GetStatus(ActionStatus *status) const override;
void HLSMainThread() ;
public:

12
receiver/PCIExpressDevice.cpp
View File

@@ -31,7 +31,7 @@ PCIExpressDevice::PCIExpressDevice(const std::string &device_name, uint16_t data
uint32_t num_buf = GetNumKernelBuffers();
if (num_buf < max_modules * (3 + 3 * 16) + 2)
if (num_buf < max_modules * (3 + 3 * 16))
throw JFJochException(JFJochExceptionCategory::PCIeError,
"Need to increase number of host-device buffers");
@@ -211,3 +211,13 @@ void PCIExpressDevice::HW_ReadInternalPacketGen(uint16_t *tmp) const {
throw JFJochException(JFJochExceptionCategory::PCIeError,
"Failed getting internal packet generator frame", errno);
}
void PCIExpressDevice::HW_LoadCalibration(uint32_t in_modules, uint32_t in_storage_cells) {
ActionConfig config{
.nmodules = in_modules,
.nstorage_cells = in_storage_cells
};
if (ioctl(fd, IOCTL_JFJOCH_LOAD_CALIB, &config) != 0)
throw JFJochException(JFJochExceptionCategory::PCIeError,
"Failed writing config", errno);
}

1
receiver/PCIExpressDevice.h
View File

@@ -15,6 +15,7 @@ class PCIExpressDevice : public FPGAAcquisitionDevice {
bool HW_IsIdle() const final;
void HW_WriteActionRegister(const ActionConfig *job) override;
void HW_ReadActionRegister(ActionConfig *job) override;
void HW_LoadCalibration(uint32_t modules, uint32_t storage_cells) override;
void FPGA_EndAction() override;
void Reset();

2
tests/FPGAIntegrationTest.cpp
View File

@@ -546,6 +546,8 @@ TEST_CASE("HLS_C_Simulation_check_2_trigger_convert", "[FPGA][Full]") {
x.PedestalG0Frames(0).NumTriggers(2).ImagesPerTrigger(5);
HLSSimulatedDevice test(0, 64);
Logger logger("bla");
test.EnableLogging(&logger);
JFCalibration c(x);
REQUIRE_NOTHROW(c.Pedestal(0, 0).LoadPedestal(pedestal_g0));