FPGA: Increase PCIe BAR size to 16 MB

2023-09-13 20:55:10 +02:00
parent 0c471b3760
commit f3e85deb31
1 changed files with 1 additions and 1 deletions
@@ -139,7 +139,7 @@ proc create_hier_cell_pcie_dma_0 { parentCell nameHier } {
   CONFIG.axi_id_width {2} \
   CONFIG.axil_master_64bit_en {false} \
   CONFIG.axilite_master_en {true} \
-   CONFIG.axilite_master_size {4} \
+   CONFIG.axilite_master_size {16} \
   CONFIG.axisten_freq {250} \
   CONFIG.cfg_mgmt_if {false} \
   CONFIG.copy_pf0 {true} \