From f3e85deb31ff5a8af324a5e29e7b3612e93b84f3 Mon Sep 17 00:00:00 2001
From: Filip Leonarski <filip.leonarski@psi.ch>
Date: Wed, 13 Sep 2023 20:55:10 +0200
Subject: [PATCH] FPGA: Increase PCIe BAR size to 16 MB

---
 fpga/scripts/pcie_dma.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/scripts/pcie_dma.tcl b/fpga/scripts/pcie_dma.tcl
index 1e141532..84cfe3b5 100644
--- a/fpga/scripts/pcie_dma.tcl
+++ b/fpga/scripts/pcie_dma.tcl
@@ -139,7 +139,7 @@ proc create_hier_cell_pcie_dma_0 { parentCell nameHier } {
    CONFIG.axi_id_width {2} \
    CONFIG.axil_master_64bit_en {false} \
    CONFIG.axilite_master_en {true} \
-   CONFIG.axilite_master_size {4} \
+   CONFIG.axilite_master_size {16} \
    CONFIG.axisten_freq {250} \
    CONFIG.cfg_mgmt_if {false} \
    CONFIG.copy_pf0 {true} \