FPGA: Build only 100G solution (no bifurcated design)
This commit is contained in:
@@ -185,8 +185,7 @@ test:x86:xia2.ssx:
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- source /usr/local/dials-v3-13-0/dials_env.sh
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- xia2.ssx image=writing_test_master.h5 space_group=P43212 unit_cell=78.551,78.551,36.914,90.000,90.000,90.000
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synthesis:vivado_pcie_200g:
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synthesis:vivado_pcie_100g:
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stage: synthesis
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variables:
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GIT_SUBMODULE_STRATEGY: recursive
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@@ -216,34 +215,3 @@ synthesis:vivado_pcie_200g:
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- cmake3 ..
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- make action_pcie
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needs: ["build:x86:gcc", "build:x86:vitis_hls", "test:x86:gcc"]
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synthesis:vivado_pcie_100g:
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stage: synthesis
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variables:
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GIT_SUBMODULE_STRATEGY: recursive
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CC: gcc
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CXX: g++
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allow_failure: true
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rules:
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- if: '$CI_PIPELINE_SOURCE == "push"'
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changes:
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- fpga/hls/*
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- fpga/hdl/*
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- fpga/scripts/*
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- fpga/xdc/*
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- common/Definitions.h
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tags:
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- vivado
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artifacts:
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paths:
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- build/fpga/*.mcs
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- build/fpga/*.bit
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expire_in: 1 week
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script:
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- source /opt/grpc/grpc.sh
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- source /opt/Xilinx/Vivado/2022.1/settings64.sh
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- mkdir -p build
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- cd build
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- cmake3 ..
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- make action_pcie_100g
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needs: ["build:x86:gcc", "build:x86:vitis_hls", "test:x86:gcc"]
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@@ -25,11 +25,6 @@ IF(VIVADO_HLS AND VIVADO)
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ADD_CUSTOM_TARGET(action_pcie DEPENDS action/hw/hdl/action_config.v hls
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COMMAND ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_SOURCE_DIR}/scripts/build_pcie_design.tcl
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COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie_200gbit VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
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)
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ADD_CUSTOM_TARGET(action_pcie_100g DEPENDS action/hw/hdl/action_config.v hls
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COMMAND ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_SOURCE_DIR}/scripts/build_pcie_design_100g.tcl
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COMMAND ${CMAKE_COMMAND} -E env FLOW=pcie_100gbit VIV_PROJECT_PATH=${CMAKE_CURRENT_BINARY_DIR}/vivado/jfjoch_pcie.xpr ${VIVADO} -notrace -mode batch -source ${CMAKE_CURRENT_BINARY_DIR}/action/scripts/synth_and_impl.tcl
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)
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ENDIF()
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@@ -224,99 +224,6 @@ if { $bCheckIPsPassed != 1 } {
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# DESIGN PROCs
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##################################################################
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# Hierarchical cell: gain_uram_0
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proc create_hier_cell_gain_uram_0 { parentCell nameHier } {
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variable script_folder
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if { $parentCell eq "" || $nameHier eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_gain_uram_0() - Empty argument(s)!"}
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return
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create cell and set as current instance
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set hier_obj [create_bd_cell -type hier $nameHier]
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current_bd_instance $hier_obj
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# Create interface pins
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi
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# Create pins
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create_bd_pin -dir I axi_aresetn
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create_bd_pin -dir I axi_clk
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# Create instance: axi_bram_ctrl_0, and set properties
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set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
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set_property -dict [ list \
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CONFIG.DATA_WIDTH {256} \
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CONFIG.READ_LATENCY {2} \
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] $axi_bram_ctrl_0
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# Create instance: axi_register_slice_0, and set properties
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set axi_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 ]
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set_property -dict [ list \
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CONFIG.REG_AR {15} \
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CONFIG.REG_AW {15} \
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CONFIG.REG_B {15} \
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CONFIG.REG_R {15} \
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CONFIG.REG_W {15} \
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CONFIG.USE_AUTOPIPELINING {1} \
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] $axi_register_slice_0
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# Create instance: blk_mem_gen_0, and set properties
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set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
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set_property -dict [ list \
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CONFIG.Assume_Synchronous_Clk {true} \
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CONFIG.EN_SAFETY_CKT {false} \
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CONFIG.Enable_B {Use_ENB_Pin} \
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CONFIG.Memory_Type {True_Dual_Port_RAM} \
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CONFIG.Operating_Mode_A {NO_CHANGE} \
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CONFIG.Operating_Mode_B {NO_CHANGE} \
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CONFIG.PRIM_type_to_Implement {URAM} \
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CONFIG.Port_B_Clock {100} \
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CONFIG.Port_B_Enable_Rate {100} \
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CONFIG.Port_B_Write_Rate {50} \
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CONFIG.READ_LATENCY_A {2} \
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CONFIG.READ_LATENCY_B {2} \
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CONFIG.Use_RSTB_Pin {true} \
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] $blk_mem_gen_0
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# Create interface connections
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connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
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connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTB]
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connect_bd_intf_net -intf_net axi_register_slice_0_M_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_register_slice_0/M_AXI]
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connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins axi_register_slice_0/S_AXI]
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# Create port connections
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connect_bd_net -net axi_aresetn_1 [get_bd_pins axi_aresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_register_slice_0/aresetn]
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connect_bd_net -net axi_clk_1 [get_bd_pins axi_clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_register_slice_0/aclk]
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# Restore current instance
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current_bd_instance $oldCurInst
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}
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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@@ -354,10 +261,6 @@ proc create_root_design { parentCell } {
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set pcie0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie0_ref ]
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set pcie1_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie1_mgt ]
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set pcie1_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie1_ref ]
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set qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0 ]
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set qsfp0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_ref ]
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@@ -365,13 +268,6 @@ proc create_root_design { parentCell } {
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CONFIG.FREQ_HZ {161132812} \
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] $qsfp0_ref
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set qsfp1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1 ]
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set qsfp1_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp1_ref ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {161132812} \
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] $qsfp1_ref
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set ref100 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ref100 ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {100000000} \
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@@ -385,8 +281,6 @@ proc create_root_design { parentCell } {
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set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
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set qsfp0_led_busy [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_busy ]
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set qsfp0_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_conn ]
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set qsfp1_led_busy [ create_bd_port -dir O -from 0 -to 0 qsfp1_led_busy ]
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set qsfp1_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp1_led_conn ]
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set satellite_gpio_0 [ create_bd_port -dir I -from 3 -to 0 -type intr satellite_gpio_0 ]
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set_property -dict [ list \
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CONFIG.PortWidth {4} \
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@@ -400,13 +294,6 @@ proc create_root_design { parentCell } {
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CONFIG.C_NUM_SW_INTR {2} \
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] $axi_intc_0
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# Create instance: axi_intc_1, and set properties
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set axi_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1 ]
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set_property -dict [ list \
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CONFIG.C_IRQ_CONNECTION {1} \
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CONFIG.C_NUM_SW_INTR {2} \
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] $axi_intc_1
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# Create instance: axi_quad_spi_0, and set properties
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set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
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set_property -dict [ list \
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@@ -444,72 +331,33 @@ proc create_root_design { parentCell } {
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# Create instance: cms_subsystem_0, and set properties
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set cms_subsystem_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem:4.0 cms_subsystem_0 ]
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# Create instance: gain_uram_0
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create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_0
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# Create instance: gain_uram_1
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create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_1
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# Create instance: gain_uram_2
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create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_2
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# Create instance: gain_uram_3
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create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_3
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# Create instance: gain_uram_4
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create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_4
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# Create instance: gain_uram_5
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create_hier_cell_gain_uram_0 [current_bd_instance .] gain_uram_5
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# Create instance: hbm_infrastructure
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create_hier_cell_hbm_infrastructure [current_bd_instance .] hbm_infrastructure
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# Create instance: jungfraujoch_0
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create_hier_cell_jungfraujoch [current_bd_instance .] jungfraujoch_0
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# Create instance: jungfraujoch_1
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create_hier_cell_jungfraujoch [current_bd_instance .] jungfraujoch_1
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# Create instance: mac_100g
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create_hier_cell_mac_100g [current_bd_instance .] mac_100g
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# Create instance: mac_100g_1
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create_hier_cell_mac_100g [current_bd_instance .] mac_100g_1
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# Create instance: one, and set properties
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set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ]
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# Create instance: pcie_dma_0
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create_hier_cell_pcie_dma_0 [current_bd_instance .] pcie_dma_0
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# Create instance: pcie_dma_1
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create_hier_cell_pcie_dma_1 [current_bd_instance .] pcie_dma_1
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# Create instance: proc_sys_reset_pcie_0, and set properties
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set proc_sys_reset_pcie_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pcie_0 ]
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set_property -dict [ list \
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CONFIG.C_EXT_RST_WIDTH {1} \
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] $proc_sys_reset_pcie_0
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# Create instance: proc_sys_reset_pcie_1, and set properties
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set proc_sys_reset_pcie_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pcie_1 ]
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set_property -dict [ list \
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CONFIG.C_EXT_RST_WIDTH {1} \
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] $proc_sys_reset_pcie_1
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# Create instance: proc_sys_reset_refclk, and set properties
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set proc_sys_reset_refclk [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_refclk ]
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set_property -dict [ list \
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CONFIG.C_EXT_RST_WIDTH {1} \
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] $proc_sys_reset_refclk
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# Create instance: proc_sys_reset_refclk1, and set properties
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set proc_sys_reset_refclk1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_refclk1 ]
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set_property -dict [ list \
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CONFIG.C_EXT_RST_WIDTH {1} \
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] $proc_sys_reset_refclk1
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# Create instance: smartconnect_0, and set properties
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set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
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set_property -dict [ list \
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@@ -518,20 +366,6 @@ proc create_root_design { parentCell } {
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CONFIG.NUM_SI {1} \
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] $smartconnect_0
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# Create instance: smartconnect_1, and set properties
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set smartconnect_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_1 ]
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set_property -dict [ list \
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CONFIG.NUM_CLKS {4} \
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CONFIG.NUM_MI {5} \
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CONFIG.NUM_SI {1} \
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] $smartconnect_1
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# Create instance: smartconnect_2, and set properties
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set smartconnect_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_2 ]
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set_property -dict [ list \
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CONFIG.NUM_CLKS {3} \
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] $smartconnect_2
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# Create instance: xlconcat_irq, and set properties
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set xlconcat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_irq ]
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@@ -559,78 +393,41 @@ proc create_root_design { parentCell } {
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_data]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_cmd]
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connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_h2c_cmd]
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connect_bd_intf_net -intf_net jungfraujoch_1_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_1/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_1/s_axis_c2h_data]
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connect_bd_intf_net -intf_net jungfraujoch_1_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_1/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_1/s_axis_c2h_cmd]
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connect_bd_intf_net -intf_net jungfraujoch_1_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_1/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_1/s_axis_h2c_cmd]
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connect_bd_intf_net -intf_net mac_100g_1_M_AXIS_100G [get_bd_intf_pins jungfraujoch_0/eth_in] [get_bd_intf_pins mac_100g/m_axis_eth_in]
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connect_bd_intf_net -intf_net mac_100g_1_m_axis_eth_in [get_bd_intf_pins jungfraujoch_1/eth_in] [get_bd_intf_pins mac_100g_1/m_axis_eth_in]
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connect_bd_intf_net -intf_net mac_100g_1_qsfp0 [get_bd_intf_ports qsfp0] [get_bd_intf_pins mac_100g/qsfp]
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connect_bd_intf_net -intf_net mac_100g_1_qsfp1 [get_bd_intf_ports qsfp1] [get_bd_intf_pins mac_100g_1/qsfp]
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connect_bd_intf_net -intf_net pcie0_ref_1 [get_bd_intf_ports pcie0_ref] [get_bd_intf_pins pcie_dma_0/pcie_refclk]
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connect_bd_intf_net -intf_net pcie1_ref_1 [get_bd_intf_ports pcie1_ref] [get_bd_intf_pins pcie_dma_1/pcie_refclk]
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connect_bd_intf_net -intf_net pcie_dma_0_M_AXI [get_bd_intf_pins pcie_dma_0/m_axi_ctrl] [get_bd_intf_pins smartconnect_0/S00_AXI]
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connect_bd_intf_net -intf_net pcie_dma_0_pcie0_mgt [get_bd_intf_ports pcie0_mgt] [get_bd_intf_pins pcie_dma_0/pcie_mgt]
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connect_bd_intf_net -intf_net pcie_dma_1_m_axi_ctrl [get_bd_intf_pins pcie_dma_1/m_axi_ctrl] [get_bd_intf_pins smartconnect_1/S00_AXI]
|
||||
connect_bd_intf_net -intf_net pcie_dma_1_pcie_mgt [get_bd_intf_ports pcie1_mgt] [get_bd_intf_pins pcie_dma_1/pcie_mgt]
|
||||
connect_bd_intf_net -intf_net qsfp0_ref_1 [get_bd_intf_ports qsfp0_ref] [get_bd_intf_pins mac_100g/qsfp_ref]
|
||||
connect_bd_intf_net -intf_net qsfp1_ref_1 [get_bd_intf_ports qsfp1_ref] [get_bd_intf_pins mac_100g_1/qsfp_ref]
|
||||
connect_bd_intf_net -intf_net ref100_1 [get_bd_intf_ports ref100] [get_bd_intf_pins clk_wiz_0/CLK_IN1_D]
|
||||
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins jungfraujoch_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
|
||||
connect_bd_intf_net -intf_net s_axi_2 [get_bd_intf_pins mac_100g/s_axi] [get_bd_intf_pins smartconnect_0/M02_AXI]
|
||||
connect_bd_intf_net -intf_net s_axi_3 [get_bd_intf_pins jungfraujoch_1/s_axi] [get_bd_intf_pins smartconnect_1/M00_AXI]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p0 [get_bd_intf_pins gain_uram_0/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p0]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p1 [get_bd_intf_pins gain_uram_1/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p1]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p2 [get_bd_intf_pins gain_uram_2/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p2]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p3 [get_bd_intf_pins gain_uram_3/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p3]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p4 [get_bd_intf_pins gain_uram_4/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p4]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p5 [get_bd_intf_pins gain_uram_5/s_axi] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p5]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p6 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_12] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p6]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p7 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_13] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p7]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p8 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_14] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p8]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p9 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_15] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p9]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p10 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_16] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p10]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_1_m_axi_d_hbm_p11 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_17] [get_bd_intf_pins jungfraujoch_1/m_axi_d_hbm_p11]
|
||||
connect_bd_intf_net -intf_net s_axis_eth_out_1 [get_bd_intf_pins jungfraujoch_1/eth_out] [get_bd_intf_pins mac_100g_1/s_axis_eth_out]
|
||||
connect_bd_intf_net -intf_net s_axis_h2c_data_1 [get_bd_intf_pins jungfraujoch_0/s_axis_h2c_data] [get_bd_intf_pins pcie_dma_0/m_axis_h2c_data]
|
||||
connect_bd_intf_net -intf_net s_axis_h2c_data_2 [get_bd_intf_pins jungfraujoch_1/s_axis_h2c_data] [get_bd_intf_pins pcie_dma_1/m_axis_h2c_data]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins smartconnect_2/S01_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins cms_subsystem_0/s_axi_ctrl]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins smartconnect_0/M03_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins smartconnect_0/M04_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins pcie_dma_0/s_axi_dma_ctrl] [get_bd_intf_pins smartconnect_0/M05_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_1_M01_AXI [get_bd_intf_pins mac_100g_1/s_axi] [get_bd_intf_pins smartconnect_1/M01_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_1_M02_AXI [get_bd_intf_pins pcie_dma_1/s_axi_dma_ctrl] [get_bd_intf_pins smartconnect_1/M02_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_1_M03_AXI [get_bd_intf_pins smartconnect_1/M03_AXI] [get_bd_intf_pins smartconnect_2/S00_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_1_M04_AXI [get_bd_intf_pins axi_intc_1/s_axi] [get_bd_intf_pins smartconnect_1/M04_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_2_M00_AXI [get_bd_intf_pins cms_subsystem_0/s_axi_ctrl] [get_bd_intf_pins smartconnect_2/M00_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_clk_1 [get_bd_pins pcie_dma_0/axi_aclk] [get_bd_pins proc_sys_reset_pcie_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk3] [get_bd_pins smartconnect_2/aclk1]
|
||||
connect_bd_net -net axi_clk_1 [get_bd_pins pcie_dma_0/axi_aclk] [get_bd_pins proc_sys_reset_pcie_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk3]
|
||||
connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins xlconcat_irq/In0]
|
||||
connect_bd_net -net cms_subsystem_0_interrupt_host [get_bd_pins cms_subsystem_0/interrupt_host] [get_bd_pins xlconcat_irq/In1]
|
||||
connect_bd_net -net hbm_infrastructure_hbm_temp_trip_1 [get_bd_ports hbm_cattrip] [get_bd_pins cms_subsystem_0/interrupt_hbm_cattrip] [get_bd_pins hbm_infrastructure/hbm_cattrip]
|
||||
connect_bd_net -net hbm_infrastructure_hbm_temperature_1 [get_bd_pins cms_subsystem_0/hbm_temp_1] [get_bd_pins hbm_infrastructure/hbm_temperature_0]
|
||||
connect_bd_net -net hbm_infrastructure_hbm_temperature_2 [get_bd_pins cms_subsystem_0/hbm_temp_2] [get_bd_pins hbm_infrastructure/hbm_temperature_1]
|
||||
connect_bd_net -net mac_100g_1_eth_busy_n [get_bd_ports qsfp1_led_busy] [get_bd_pins mac_100g_1/eth_busy_n]
|
||||
connect_bd_net -net mac_100g_1_stat_rx_aligned_n [get_bd_ports qsfp1_led_conn] [get_bd_pins mac_100g_1/stat_rx_aligned_n]
|
||||
connect_bd_net -net mac_100g_eth_busy_n [get_bd_ports qsfp0_led_busy] [get_bd_pins mac_100g/eth_busy_n]
|
||||
connect_bd_net -net mac_100g_stat_rx_aligned_n [get_bd_ports qsfp0_led_conn] [get_bd_pins mac_100g/stat_rx_aligned_n]
|
||||
connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_intc_1/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins proc_sys_reset_refclk1/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2] [get_bd_pins smartconnect_1/aclk1] [get_bd_pins smartconnect_2/aclk]
|
||||
connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins mac_100g_1/refclk100] [get_bd_pins smartconnect_0/aclk1] [get_bd_pins smartconnect_1/aclk2]
|
||||
connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins gain_uram_0/axi_clk] [get_bd_pins gain_uram_1/axi_clk] [get_bd_pins gain_uram_2/axi_clk] [get_bd_pins gain_uram_3/axi_clk] [get_bd_pins gain_uram_4/axi_clk] [get_bd_pins gain_uram_5/axi_clk] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch_0/axi_clk] [get_bd_pins jungfraujoch_1/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins mac_100g_1/axiclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins pcie_dma_1/refclk200] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk]
|
||||
connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins cms_subsystem_0/aresetn_ctrl] [get_bd_pins smartconnect_2/aresetn] [get_bd_pins proc_sys_reset_pcie_0/dcm_locked] [get_bd_pins proc_sys_reset_pcie_1/dcm_locked] [get_bd_pins proc_sys_reset_refclk/dcm_locked] [get_bd_pins proc_sys_reset_refclk1/dcm_locked]
|
||||
connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_intc_1/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins proc_sys_reset_refclk1/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2]
|
||||
connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins smartconnect_0/aclk1]
|
||||
connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch_0/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins smartconnect_0/aclk]
|
||||
connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins cms_subsystem_0/aresetn_ctrl] [get_bd_pins proc_sys_reset_pcie_0/dcm_locked] [get_bd_pins proc_sys_reset_refclk/dcm_locked]
|
||||
connect_bd_net -net pcie_dma_0_axi_aresetn [get_bd_pins pcie_dma_0/axi_aresetn] [get_bd_pins proc_sys_reset_pcie_0/ext_reset_in] [get_bd_pins proc_sys_reset_refclk/ext_reset_in] [get_bd_pins smartconnect_0/aresetn]
|
||||
connect_bd_net -net pcie_dma_1_axi_aclk [get_bd_pins pcie_dma_1/axi_aclk] [get_bd_pins proc_sys_reset_pcie_1/slowest_sync_clk] [get_bd_pins smartconnect_1/aclk3] [get_bd_pins smartconnect_2/aclk2]
|
||||
connect_bd_net -net pcie_dma_1_axi_aresetn [get_bd_pins pcie_dma_1/axi_aresetn] [get_bd_pins proc_sys_reset_pcie_1/ext_reset_in] [get_bd_pins proc_sys_reset_refclk1/ext_reset_in] [get_bd_pins smartconnect_1/aresetn]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins pcie_dma_0/pcie_perstn] [get_bd_pins pcie_dma_1/pcie_perstn]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins pcie_dma_0/pcie_perstn]
|
||||
connect_bd_net -net proc_sys_reset_pcie_0_interconnect_aresetn [get_bd_pins pcie_dma_0/axi_clk_resetn] [get_bd_pins proc_sys_reset_pcie_0/interconnect_aresetn]
|
||||
connect_bd_net -net proc_sys_reset_pcie_1_interconnect_aresetn [get_bd_pins pcie_dma_1/axi_clk_resetn] [get_bd_pins proc_sys_reset_pcie_1/interconnect_aresetn]
|
||||
connect_bd_net -net proc_sys_reset_refclk1_interconnect_aresetn [get_bd_pins gain_uram_0/axi_aresetn] [get_bd_pins gain_uram_1/axi_aresetn] [get_bd_pins gain_uram_2/axi_aresetn] [get_bd_pins gain_uram_3/axi_aresetn] [get_bd_pins gain_uram_4/axi_aresetn] [get_bd_pins gain_uram_5/axi_aresetn] [get_bd_pins jungfraujoch_1/axi_rst_n] [get_bd_pins mac_100g_1/ap_rst_n] [get_bd_pins pcie_dma_1/refclk200_resetn] [get_bd_pins proc_sys_reset_refclk1/interconnect_aresetn]
|
||||
connect_bd_net -net proc_sys_reset_refclk1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn] [get_bd_pins hbm_infrastructure/axi_resetn_1] [get_bd_pins jungfraujoch_1/ap_rst_n] [get_bd_pins mac_100g_1/resetn] [get_bd_pins proc_sys_reset_refclk1/peripheral_aresetn]
|
||||
connect_bd_net -net proc_sys_reset_refclk_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins hbm_infrastructure/axi_resetn] [get_bd_pins jungfraujoch_0/ap_rst_n] [get_bd_pins mac_100g/ap_rst_n] [get_bd_pins proc_sys_reset_refclk/peripheral_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_pins jungfraujoch_0/axi_rst_n] [get_bd_pins mac_100g/resetn] [get_bd_pins pcie_dma_0/refclk200_resetn] [get_bd_pins proc_sys_reset_refclk/interconnect_aresetn]
|
||||
connect_bd_net -net satellite_gpio_0_1 [get_bd_ports satellite_gpio_0] [get_bd_pins cms_subsystem_0/satellite_gpio]
|
||||
connect_bd_net -net usr_irq_req_1 [get_bd_pins axi_intc_0/irq] [get_bd_pins pcie_dma_0/usr_irq_req]
|
||||
connect_bd_net -net usr_irq_req_2 [get_bd_pins axi_intc_1/irq] [get_bd_pins pcie_dma_1/usr_irq_req]
|
||||
connect_bd_net -net xlconcat_irq_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins axi_intc_1/intr] [get_bd_pins xlconcat_irq/dout]
|
||||
connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins zero/dout]
|
||||
|
||||
@@ -646,24 +443,6 @@ proc create_root_design { parentCell } {
|
||||
assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force
|
||||
assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force
|
||||
|
||||
assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/action_config_0/s_axi/reg0] -force
|
||||
assign_bd_address -offset 0x00020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs mac_100g_1/cmac_usplus_0/s_axi/Reg] -force
|
||||
assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/mailbox_0/S0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_intc_1/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/axi_bram_ctrl_calibration_addr/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_1/axi_firewall_0/S_AXI_CTL/Control] -force
|
||||
assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_1/xdma_0/S_AXI_LITE/CTL0] -force
|
||||
assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force
|
||||
assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_1/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_1/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_1/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force
|
||||
|
||||
assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p0] [get_bd_addr_segs gain_uram_0/axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p1] [get_bd_addr_segs gain_uram_1/axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p2] [get_bd_addr_segs gain_uram_2/axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p3] [get_bd_addr_segs gain_uram_3/axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p4] [get_bd_addr_segs gain_uram_4/axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00000000 -range 0x00200000 -target_address_space [get_bd_addr_spaces jungfraujoch_1/jf_conversion_0/Data_m_axi_d_hbm_p5] [get_bd_addr_segs gain_uram_5/axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
assign_bd_address
|
||||
|
||||
set_property -dict [ list \
|
||||
@@ -671,21 +450,11 @@ proc create_root_design { parentCell } {
|
||||
CONFIG.GT_GROUP_SELECT {X0Y24~X0Y27} \
|
||||
] [get_bd_cells mac_100g/cmac_usplus_0]
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y4} \
|
||||
CONFIG.GT_GROUP_SELECT {X0Y28~X0Y31} \
|
||||
] [get_bd_cells mac_100g_1/cmac_usplus_0]
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \
|
||||
CONFIG.DESIGN_NUMBER {0} \
|
||||
] [get_bd_cells jungfraujoch_0/action_config_0]
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.MAX_MODULES_FPGA_PARAM {0x00000004} \
|
||||
CONFIG.DESIGN_NUMBER {1} \
|
||||
] [get_bd_cells jungfraujoch_1/action_config_0]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
|
||||
@@ -1,471 +0,0 @@
|
||||
## Copyright (2019-2022) Paul Scherrer Institute
|
||||
## SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
|
||||
################################################################
|
||||
# This is a generated script based on design: jfjoch_pcie
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2022.1
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source jfjoch_pcie_script.tcl
|
||||
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# gen_xdma_descriptor, action_config, check_eth_busy, resetn_sync
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xcvu35p-fsvh2104-2-e
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name jfjoch_pcie
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_intc:4.1\
|
||||
xilinx.com:ip:axi_quad_spi:3.2\
|
||||
xilinx.com:ip:clk_wiz:6.0\
|
||||
xilinx.com:ip:cms_subsystem:4.0\
|
||||
xilinx.com:ip:xlconstant:1.1\
|
||||
xilinx.com:ip:proc_sys_reset:5.0\
|
||||
xilinx.com:ip:smartconnect:1.0\
|
||||
xilinx.com:ip:xlconcat:2.1\
|
||||
xilinx.com:ip:axi_protocol_converter:2.1\
|
||||
xilinx.com:ip:axi_register_slice:2.1\
|
||||
xilinx.com:ip:hbm:1.0\
|
||||
xilinx.com:ip:util_vector_logic:2.0\
|
||||
xilinx.com:ip:axi_bram_ctrl:4.1\
|
||||
xilinx.com:ip:axis_data_fifo:2.0\
|
||||
xilinx.com:ip:axis_register_slice:1.1\
|
||||
xilinx.com:ip:blk_mem_gen:8.4\
|
||||
psi.ch:hls:data_collection_fsm:1.0\
|
||||
psi.ch:hls:host_writer:1.0\
|
||||
psi.ch:hls:internal_packet_generator:1.0\
|
||||
psi.ch:hls:jf_conversion:1.0\
|
||||
psi.ch:hls:load_calibration:1.0\
|
||||
xilinx.com:ip:mailbox:2.1\
|
||||
psi.ch:hls:timer_hbm:1.0\
|
||||
psi.ch:hls:timer_host:1.0\
|
||||
xilinx.com:ip:cmac_usplus:3.1\
|
||||
xilinx.com:ip:axi_firewall:1.2\
|
||||
xilinx.com:ip:axis_clock_converter:1.1\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
xilinx.com:ip:xdma:4.1\
|
||||
psi.ch:hls:arp:1.0\
|
||||
xilinx.com:ip:axis_switch:1.1\
|
||||
psi.ch:hls:ethernet:1.0\
|
||||
psi.ch:hls:icmp:1.0\
|
||||
psi.ch:hls:ipv4:1.0\
|
||||
psi.ch:hls:sls_detector:1.0\
|
||||
psi.ch:hls:udp:1.0\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# CHECK Modules
|
||||
##################################################################
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
gen_xdma_descriptor\
|
||||
action_config\
|
||||
check_eth_busy\
|
||||
resetn_sync\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
|
||||
|
||||
foreach mod_vlnv $list_check_mods {
|
||||
if { [can_resolve_reference $mod_vlnv] == 0 } {
|
||||
lappend list_mods_missing $mod_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_mods_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
|
||||
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set pcie0_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie0_mgt ]
|
||||
|
||||
set pcie0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie0_ref ]
|
||||
|
||||
set qsfp0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp0 ]
|
||||
|
||||
set qsfp0_ref [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp0_ref ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {161132812} \
|
||||
] $qsfp0_ref
|
||||
|
||||
set ref100 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ref100 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {100000000} \
|
||||
] $ref100
|
||||
|
||||
set satellite_uart_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 satellite_uart_0 ]
|
||||
|
||||
|
||||
# Create ports
|
||||
set hbm_cattrip [ create_bd_port -dir O -from 0 -to 0 hbm_cattrip ]
|
||||
set pcie_perstn [ create_bd_port -dir I -type rst pcie_perstn ]
|
||||
set qsfp0_led_busy [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_busy ]
|
||||
set qsfp0_led_conn [ create_bd_port -dir O -from 0 -to 0 qsfp0_led_conn ]
|
||||
set satellite_gpio_0 [ create_bd_port -dir I -from 3 -to 0 -type intr satellite_gpio_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.PortWidth {4} \
|
||||
CONFIG.SENSITIVITY {EDGE_RISING} \
|
||||
] $satellite_gpio_0
|
||||
|
||||
# Create instance: axi_intc_0, and set properties
|
||||
set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_IRQ_CONNECTION {1} \
|
||||
CONFIG.C_NUM_SW_INTR {2} \
|
||||
] $axi_intc_0
|
||||
|
||||
# Create instance: axi_quad_spi_0, and set properties
|
||||
set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_FIFO_DEPTH {256} \
|
||||
CONFIG.C_SCK_RATIO {2} \
|
||||
CONFIG.C_SPI_MEMORY {2} \
|
||||
CONFIG.C_SPI_MODE {2} \
|
||||
CONFIG.C_USE_STARTUP {1} \
|
||||
CONFIG.C_USE_STARTUP_INT {1} \
|
||||
] $axi_quad_spi_0
|
||||
|
||||
# Create instance: clk_wiz_0, and set properties
|
||||
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CLKOUT1_JITTER {132.683} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
|
||||
CONFIG.CLKOUT2_JITTER {115.831} \
|
||||
CONFIG.CLKOUT2_PHASE_ERROR {87.180} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT3_JITTER {102.086} \
|
||||
CONFIG.CLKOUT3_PHASE_ERROR {87.180} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} \
|
||||
CONFIG.CLKOUT3_USED {true} \
|
||||
CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \
|
||||
CONFIG.MMCM_CLKOUT1_DIVIDE {12} \
|
||||
CONFIG.MMCM_CLKOUT2_DIVIDE {6} \
|
||||
CONFIG.NUM_OUT_CLKS {3} \
|
||||
CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
|
||||
CONFIG.RESET_PORT {reset} \
|
||||
CONFIG.RESET_TYPE {ACTIVE_HIGH} \
|
||||
CONFIG.USE_LOCKED {false} \
|
||||
CONFIG.USE_RESET {false} \
|
||||
] $clk_wiz_0
|
||||
|
||||
# Create instance: cms_subsystem_0, and set properties
|
||||
set cms_subsystem_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem:4.0 cms_subsystem_0 ]
|
||||
|
||||
# Create instance: hbm_infrastructure
|
||||
create_hier_cell_hbm_infrastructure [current_bd_instance .] hbm_infrastructure
|
||||
|
||||
# Create instance: jungfraujoch_0
|
||||
create_hier_cell_jungfraujoch [current_bd_instance .] jungfraujoch_0
|
||||
|
||||
# Create instance: mac_100g
|
||||
create_hier_cell_mac_100g [current_bd_instance .] mac_100g
|
||||
|
||||
# Create instance: one, and set properties
|
||||
set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ]
|
||||
|
||||
# Create instance: pcie_dma_0
|
||||
create_hier_cell_pcie_dma_0 [current_bd_instance .] pcie_dma_0
|
||||
|
||||
# Create instance: proc_sys_reset_pcie_0, and set properties
|
||||
set proc_sys_reset_pcie_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_pcie_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_EXT_RST_WIDTH {1} \
|
||||
] $proc_sys_reset_pcie_0
|
||||
|
||||
# Create instance: proc_sys_reset_refclk, and set properties
|
||||
set proc_sys_reset_refclk [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_refclk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_EXT_RST_WIDTH {1} \
|
||||
] $proc_sys_reset_refclk
|
||||
|
||||
# Create instance: smartconnect_0, and set properties
|
||||
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_CLKS {4} \
|
||||
CONFIG.NUM_MI {6} \
|
||||
CONFIG.NUM_SI {1} \
|
||||
] $smartconnect_0
|
||||
|
||||
# Create instance: xlconcat_irq, and set properties
|
||||
set xlconcat_irq [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_irq ]
|
||||
|
||||
# Create instance: zero, and set properties
|
||||
set zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CONST_VAL {0} \
|
||||
] $zero
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net S_AXIS_100G_1 [get_bd_intf_pins jungfraujoch_0/eth_out] [get_bd_intf_pins mac_100g/s_axis_eth_out]
|
||||
connect_bd_intf_net -intf_net cms_subsystem_0_satellite_uart [get_bd_intf_ports satellite_uart_0] [get_bd_intf_pins cms_subsystem_0/satellite_uart]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p0 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_0] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p0]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p1 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_1] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p1]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p2 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_2] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p2]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p3 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_3] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p3]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p4 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_4] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p4]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p5 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_5] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p5]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p6 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_6] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p6]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p7 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_7] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p7]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p8 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_8] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p8]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p9 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_9] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p9]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p10 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_10] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p10]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axi_d_hbm_p11 [get_bd_intf_pins hbm_infrastructure/s_axi_hbm_11] [get_bd_intf_pins jungfraujoch_0/m_axi_d_hbm_p11]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_data [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_data] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_data]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_c2h_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_c2h_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_c2h_cmd]
|
||||
connect_bd_intf_net -intf_net jungfraujoch_0_m_axis_h2c_datamover_cmd [get_bd_intf_pins jungfraujoch_0/m_axis_h2c_datamover_cmd] [get_bd_intf_pins pcie_dma_0/s_axis_h2c_cmd]
|
||||
connect_bd_intf_net -intf_net mac_100g_1_M_AXIS_100G [get_bd_intf_pins jungfraujoch_0/eth_in] [get_bd_intf_pins mac_100g/m_axis_eth_in]
|
||||
connect_bd_intf_net -intf_net mac_100g_1_qsfp0 [get_bd_intf_ports qsfp0] [get_bd_intf_pins mac_100g/qsfp]
|
||||
connect_bd_intf_net -intf_net pcie0_ref_1 [get_bd_intf_ports pcie0_ref] [get_bd_intf_pins pcie_dma_0/pcie_refclk]
|
||||
connect_bd_intf_net -intf_net pcie_dma_0_M_AXI [get_bd_intf_pins pcie_dma_0/m_axi_ctrl] [get_bd_intf_pins smartconnect_0/S00_AXI]
|
||||
connect_bd_intf_net -intf_net pcie_dma_0_pcie0_mgt [get_bd_intf_ports pcie0_mgt] [get_bd_intf_pins pcie_dma_0/pcie_mgt]
|
||||
connect_bd_intf_net -intf_net qsfp0_ref_1 [get_bd_intf_ports qsfp0_ref] [get_bd_intf_pins mac_100g/qsfp_ref]
|
||||
connect_bd_intf_net -intf_net ref100_1 [get_bd_intf_ports ref100] [get_bd_intf_pins clk_wiz_0/CLK_IN1_D]
|
||||
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins jungfraujoch_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
|
||||
connect_bd_intf_net -intf_net s_axi_2 [get_bd_intf_pins mac_100g/s_axi] [get_bd_intf_pins smartconnect_0/M02_AXI]
|
||||
connect_bd_intf_net -intf_net s_axis_h2c_data_1 [get_bd_intf_pins jungfraujoch_0/s_axis_h2c_data] [get_bd_intf_pins pcie_dma_0/m_axis_h2c_data]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins smartconnect_0/M01_AXI] [get_bd_intf_pins cms_subsystem_0/s_axi_ctrl]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins smartconnect_0/M03_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins smartconnect_0/M04_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins pcie_dma_0/s_axi_dma_ctrl] [get_bd_intf_pins smartconnect_0/M05_AXI]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net axi_clk_1 [get_bd_pins pcie_dma_0/axi_aclk] [get_bd_pins proc_sys_reset_pcie_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk3]
|
||||
connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins xlconcat_irq/In0]
|
||||
connect_bd_net -net cms_subsystem_0_interrupt_host [get_bd_pins cms_subsystem_0/interrupt_host] [get_bd_pins xlconcat_irq/In1]
|
||||
connect_bd_net -net hbm_infrastructure_hbm_temp_trip_1 [get_bd_ports hbm_cattrip] [get_bd_pins cms_subsystem_0/interrupt_hbm_cattrip] [get_bd_pins hbm_infrastructure/hbm_cattrip]
|
||||
connect_bd_net -net hbm_infrastructure_hbm_temperature_1 [get_bd_pins cms_subsystem_0/hbm_temp_1] [get_bd_pins hbm_infrastructure/hbm_temperature_0]
|
||||
connect_bd_net -net hbm_infrastructure_hbm_temperature_2 [get_bd_pins cms_subsystem_0/hbm_temp_2] [get_bd_pins hbm_infrastructure/hbm_temperature_1]
|
||||
connect_bd_net -net mac_100g_eth_busy_n [get_bd_ports qsfp0_led_busy] [get_bd_pins mac_100g/eth_busy_n]
|
||||
connect_bd_net -net mac_100g_stat_rx_aligned_n [get_bd_ports qsfp0_led_conn] [get_bd_pins mac_100g/stat_rx_aligned_n]
|
||||
connect_bd_net -net net_refclk50 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_intc_1/s_axi_aclk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins cms_subsystem_0/aclk_ctrl] [get_bd_pins proc_sys_reset_refclk/slowest_sync_clk] [get_bd_pins proc_sys_reset_refclk1/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk2]
|
||||
connect_bd_net -net net_refclk100 [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins hbm_infrastructure/refclk100] [get_bd_pins mac_100g/refclk100] [get_bd_pins smartconnect_0/aclk1]
|
||||
connect_bd_net -net net_refclk200 [get_bd_pins clk_wiz_0/clk_out3] [get_bd_pins hbm_infrastructure/axi_clk] [get_bd_pins jungfraujoch_0/axi_clk] [get_bd_pins mac_100g/axiclk] [get_bd_pins pcie_dma_0/refclk200] [get_bd_pins smartconnect_0/aclk]
|
||||
connect_bd_net -net one_dout [get_bd_pins one/dout] [get_bd_pins cms_subsystem_0/aresetn_ctrl] [get_bd_pins proc_sys_reset_pcie_0/dcm_locked] [get_bd_pins proc_sys_reset_refclk/dcm_locked]
|
||||
connect_bd_net -net pcie_dma_0_axi_aresetn [get_bd_pins pcie_dma_0/axi_aresetn] [get_bd_pins proc_sys_reset_pcie_0/ext_reset_in] [get_bd_pins proc_sys_reset_refclk/ext_reset_in] [get_bd_pins smartconnect_0/aresetn]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_ports pcie_perstn] [get_bd_pins pcie_dma_0/pcie_perstn]
|
||||
connect_bd_net -net proc_sys_reset_pcie_0_interconnect_aresetn [get_bd_pins pcie_dma_0/axi_clk_resetn] [get_bd_pins proc_sys_reset_pcie_0/interconnect_aresetn]
|
||||
connect_bd_net -net proc_sys_reset_refclk_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins hbm_infrastructure/axi_resetn] [get_bd_pins jungfraujoch_0/ap_rst_n] [get_bd_pins mac_100g/ap_rst_n] [get_bd_pins proc_sys_reset_refclk/peripheral_aresetn]
|
||||
connect_bd_net -net resetn_1 [get_bd_pins jungfraujoch_0/axi_rst_n] [get_bd_pins mac_100g/resetn] [get_bd_pins pcie_dma_0/refclk200_resetn] [get_bd_pins proc_sys_reset_refclk/interconnect_aresetn]
|
||||
connect_bd_net -net satellite_gpio_0_1 [get_bd_ports satellite_gpio_0] [get_bd_pins cms_subsystem_0/satellite_gpio]
|
||||
connect_bd_net -net usr_irq_req_1 [get_bd_pins axi_intc_0/irq] [get_bd_pins pcie_dma_0/usr_irq_req]
|
||||
connect_bd_net -net xlconcat_irq_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins axi_intc_1/intr] [get_bd_pins xlconcat_irq/dout]
|
||||
connect_bd_net -net zero_dout [get_bd_pins axi_quad_spi_0/usrcclkts] [get_bd_pins zero/dout]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/action_config_0/s_axi/reg0] -force
|
||||
assign_bd_address -offset 0x00020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs mac_100g/cmac_usplus_0/s_axi/Reg] -force
|
||||
assign_bd_address -offset 0x00030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/mailbox_0/S0_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] -force
|
||||
assign_bd_address -offset 0x00050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x00060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_calibration_addr/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/axi_firewall_0/S_AXI_CTL/Control] -force
|
||||
assign_bd_address -offset 0x00090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs pcie_dma_0/xdma_0/S_AXI_LITE/CTL0] -force
|
||||
assign_bd_address -offset 0x000C0000 -range 0x00040000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs cms_subsystem_0/s_axi_ctrl/Mem] -force
|
||||
assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces pcie_dma_0/xdma_0/M_AXI_LITE] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_0/S_AXI/Mem0] -force
|
||||
assign_bd_address -offset 0x00100000 -range 0x00100000 -target_address_space [get_bd_addr_spaces jungfraujoch_0/internal_packet_generator_0/Data_m_axi_frame] [get_bd_addr_segs jungfraujoch_0/axi_bram_ctrl_internal_packet_generator_1/S_AXI/Mem0] -force
|
||||
assign_bd_address
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y3} \
|
||||
CONFIG.GT_GROUP_SELECT {X0Y24~X0Y27} \
|
||||
] [get_bd_cells mac_100g/cmac_usplus_0]
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.MAX_MODULES_FPGA_PARAM {0x00000010} \
|
||||
CONFIG.DESIGN_NUMBER {0} \
|
||||
] [get_bd_cells jungfraujoch_0/action_config_0]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
save_bd_design
|
||||
validate_bd_design
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
@@ -1,65 +0,0 @@
|
||||
## Copyright (2019-2022) Paul Scherrer Institute
|
||||
## SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
|
||||
set origin_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set project [create_project -force -part "xcu55c-fsvh2892-2L-e" "jfjoch_pcie" "vivado"]
|
||||
current_project $project
|
||||
|
||||
# Get the directory path for the new project
|
||||
set proj_dir [get_property directory $project]
|
||||
|
||||
set_property ip_repo_paths [concat [get_property ip_repo_paths [current_project]] "action/ip"] [current_project]
|
||||
|
||||
update_ip_catalog
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
set source_set [get_filesets sources_1]
|
||||
|
||||
set hdl_files [list \
|
||||
[file normalize "action/hw/hdl/action_config.v"] \
|
||||
[file normalize "action/hw/hdl/resetn_sync.v"] \
|
||||
[file normalize "action/hw/hdl/check_eth_busy.v"] \
|
||||
[file normalize "action/hw/hdl/gen_xdma_descriptor.v"] \
|
||||
]
|
||||
|
||||
if { [llength $hdl_files] > 0 } {
|
||||
add_files -norecurse -fileset $source_set $hdl_files
|
||||
}
|
||||
|
||||
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
set constraint_set [get_filesets constrs_1]
|
||||
|
||||
# Add constraints files
|
||||
# Put target .xdc as LAST in list
|
||||
set constraint_files [list \
|
||||
[file normalize "$origin_dir/../xdc/pcie_u55c.xdc"] \
|
||||
[file normalize "$origin_dir/../xdc/pcie_timing.xdc"] \
|
||||
]
|
||||
|
||||
add_files -norecurse -fileset $constraint_set $constraint_files
|
||||
set_property "target_constrs_file" [lindex $constraint_files 0] $constraint_set
|
||||
|
||||
source $origin_dir/network_stack.tcl
|
||||
source $origin_dir/hbm_u55c.tcl
|
||||
source $origin_dir/jfjoch.tcl
|
||||
source $origin_dir/pcie_dma.tcl
|
||||
source $origin_dir/mac_100g_pcie.tcl
|
||||
source $origin_dir/bd_pcie_100g.tcl >> build_pcie.log
|
||||
|
||||
make_wrapper -files [get_files "vivado/jfjoch_pcie.srcs/sources_1/bd/jfjoch_pcie/jfjoch_pcie.bd"] -top >> make_wrapper.log
|
||||
add_files -norecurse "vivado/jfjoch_pcie.gen/sources_1/bd/jfjoch_pcie/hdl/jfjoch_pcie_wrapper.v"
|
||||
set_property top jfjoch_pcie_wrapper [current_fileset]
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property synth_checkpoint_mode None [get_files vivado/jfjoch_pcie.srcs/sources_1/bd/jfjoch_pcie/jfjoch_pcie.bd]
|
||||
generate_target all [get_files vivado/jfjoch_pcie.srcs/sources_1/bd/jfjoch_pcie/jfjoch_pcie.bd] >> generate_target.log
|
||||
|
||||
set_property flow {Vivado Synthesis 2022} [get_runs synth_1]
|
||||
set_property strategy Flow_PerfOptimized_high [get_runs synth_1]
|
||||
set_property strategy Performance_ExploreWithRemap [get_runs impl_1]
|
||||
@@ -220,223 +220,3 @@ proc create_hier_cell_pcie_dma_0 { parentCell nameHier } {
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
# Hierarchical cell: pcie_dma_1
|
||||
proc create_hier_cell_pcie_dma_1 { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_pcie_dma() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ctrl
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_h2c_data
|
||||
|
||||
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_mgt
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_dma_ctrl
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_c2h_cmd
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_c2h_data
|
||||
|
||||
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_h2c_cmd
|
||||
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir O -type clk axi_aclk
|
||||
create_bd_pin -dir O -type rst axi_aresetn
|
||||
create_bd_pin -dir I -type rst axi_clk_resetn
|
||||
create_bd_pin -dir I -type rst pcie_perstn
|
||||
create_bd_pin -dir I -type clk refclk200
|
||||
create_bd_pin -dir I -type rst refclk200_resetn
|
||||
create_bd_pin -dir I usr_irq_req
|
||||
|
||||
# Create instance: axi_firewall_0, and set properties
|
||||
set axi_firewall_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_firewall:1.2 axi_firewall_0 ]
|
||||
|
||||
# Create instance: axis_clock_converter_c2h_cmd, and set properties
|
||||
set axis_clock_converter_c2h_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_c2h_cmd ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {3} \
|
||||
] $axis_clock_converter_c2h_cmd
|
||||
|
||||
# Create instance: axis_clock_converter_c2h_data, and set properties
|
||||
set axis_clock_converter_c2h_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_c2h_data ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {3} \
|
||||
] $axis_clock_converter_c2h_data
|
||||
|
||||
# Create instance: axis_clock_converter_h2c_cmd, and set properties
|
||||
set axis_clock_converter_h2c_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_h2c_cmd ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {3} \
|
||||
] $axis_clock_converter_h2c_cmd
|
||||
|
||||
# Create instance: axis_clock_converter_h2c_data, and set properties
|
||||
set axis_clock_converter_h2c_data [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_clock_converter:1.1 axis_clock_converter_h2c_data ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.SYNCHRONIZATION_STAGES {3} \
|
||||
] $axis_clock_converter_h2c_data
|
||||
|
||||
# Create instance: gen_xdma_descriptor_c2h, and set properties
|
||||
set block_name gen_xdma_descriptor
|
||||
set block_cell_name gen_xdma_descriptor_c2h
|
||||
if { [catch {set gen_xdma_descriptor_c2h [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $gen_xdma_descriptor_c2h eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: gen_xdma_descriptor_h2c, and set properties
|
||||
set block_name gen_xdma_descriptor
|
||||
set block_cell_name gen_xdma_descriptor_h2c
|
||||
if { [catch {set gen_xdma_descriptor_h2c [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $gen_xdma_descriptor_h2c eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: pcie_clk_buf_inst, and set properties
|
||||
set pcie_clk_buf_inst [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 pcie_clk_buf_inst ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {IBUFDSGTE} \
|
||||
] $pcie_clk_buf_inst
|
||||
|
||||
# Create instance: smartconnect_0, and set properties
|
||||
set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_MI {2} \
|
||||
CONFIG.NUM_SI {1} \
|
||||
] $smartconnect_0
|
||||
|
||||
# Create instance: xdma_0, and set properties
|
||||
set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.INS_LOSS_NYQ {15} \
|
||||
CONFIG.PF0_DEVICE_ID_mqdma {9048} \
|
||||
CONFIG.PF0_SRIOV_VF_DEVICE_ID {A048} \
|
||||
CONFIG.PF1_SRIOV_VF_DEVICE_ID {A148} \
|
||||
CONFIG.PF2_DEVICE_ID_mqdma {9248} \
|
||||
CONFIG.PF2_SRIOV_VF_DEVICE_ID {A248} \
|
||||
CONFIG.PF3_DEVICE_ID_mqdma {9348} \
|
||||
CONFIG.PF3_SRIOV_VF_DEVICE_ID {A348} \
|
||||
CONFIG.axi_data_width {512_bit} \
|
||||
CONFIG.axi_id_width {2} \
|
||||
CONFIG.axil_master_64bit_en {false} \
|
||||
CONFIG.axilite_master_en {true} \
|
||||
CONFIG.axilite_master_size {4} \
|
||||
CONFIG.axisten_freq {250} \
|
||||
CONFIG.cfg_mgmt_if {false} \
|
||||
CONFIG.copy_pf0 {true} \
|
||||
CONFIG.coreclk_freq {500} \
|
||||
CONFIG.dsc_bypass_rd {0001} \
|
||||
CONFIG.dsc_bypass_wr {0001} \
|
||||
CONFIG.en_gt_selection {true} \
|
||||
CONFIG.ins_loss_profile {Add-in_Card} \
|
||||
CONFIG.mode_selection {Advanced} \
|
||||
CONFIG.pcie_blk_locn {PCIE4C_X1Y0} \
|
||||
CONFIG.pf0_base_class_menu {Processing_accelerators} \
|
||||
CONFIG.pf0_class_code {120000} \
|
||||
CONFIG.pf0_class_code_base {12} \
|
||||
CONFIG.pf0_class_code_interface {00} \
|
||||
CONFIG.pf0_class_code_sub {00} \
|
||||
CONFIG.pf0_device_id {9048} \
|
||||
CONFIG.pf0_msix_cap_pba_bir {BAR_1} \
|
||||
CONFIG.pf0_msix_cap_pba_offset {00008FE0} \
|
||||
CONFIG.pf0_msix_cap_table_bir {BAR_1} \
|
||||
CONFIG.pf0_msix_cap_table_offset {00008000} \
|
||||
CONFIG.pf0_msix_cap_table_size {01F} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.pf0_sub_class_interface_menu {Unknown} \
|
||||
CONFIG.pf0_subsystem_id {5232} \
|
||||
CONFIG.pf0_subsystem_vendor_id {10EE} \
|
||||
CONFIG.pf1_msix_cap_pba_offset {00000000} \
|
||||
CONFIG.pf1_msix_cap_table_offset {00000000} \
|
||||
CONFIG.pf1_msix_cap_table_size {000} \
|
||||
CONFIG.pl_link_cap_max_link_speed {16.0_GT/s} \
|
||||
CONFIG.pl_link_cap_max_link_width {X8} \
|
||||
CONFIG.plltype {QPLL0} \
|
||||
CONFIG.runbit_fix {false} \
|
||||
CONFIG.select_quad {GTY_Quad_225} \
|
||||
CONFIG.vendor_id {10EE} \
|
||||
CONFIG.xdma_axi_intf_mm {AXI_Stream} \
|
||||
CONFIG.xdma_axilite_slave {true} \
|
||||
CONFIG.xdma_wnum_chnl {1} \
|
||||
] $xdma_0
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axis_c2h_cmd] [get_bd_intf_pins axis_clock_converter_c2h_cmd/S_AXIS]
|
||||
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axi_ctrl] [get_bd_intf_pins axi_firewall_0/M_AXI]
|
||||
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins pcie_mgt] [get_bd_intf_pins xdma_0/pcie_mgt]
|
||||
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins s_axis_c2h_data] [get_bd_intf_pins axis_clock_converter_c2h_data/S_AXIS]
|
||||
connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins pcie_refclk] [get_bd_intf_pins pcie_clk_buf_inst/CLK_IN_D]
|
||||
connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins m_axis_h2c_data] [get_bd_intf_pins axis_clock_converter_h2c_data/M_AXIS]
|
||||
connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins s_axis_h2c_cmd] [get_bd_intf_pins axis_clock_converter_h2c_cmd/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_clock_converter_c2h_cmd_M_AXIS [get_bd_intf_pins axis_clock_converter_c2h_cmd/M_AXIS] [get_bd_intf_pins gen_xdma_descriptor_c2h/S_AXIS]
|
||||
connect_bd_intf_net -intf_net axis_clock_converter_c2h_data_M_AXIS [get_bd_intf_pins axis_clock_converter_c2h_data/M_AXIS] [get_bd_intf_pins xdma_0/S_AXIS_C2H_0]
|
||||
connect_bd_intf_net -intf_net axis_clock_converter_h2c_cmd_M_AXIS [get_bd_intf_pins axis_clock_converter_h2c_cmd/M_AXIS] [get_bd_intf_pins gen_xdma_descriptor_h2c/S_AXIS]
|
||||
connect_bd_intf_net -intf_net s_axi_dma_ctrl_1 [get_bd_intf_pins s_axi_dma_ctrl] [get_bd_intf_pins xdma_0/S_AXI_LITE]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_firewall_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
|
||||
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_firewall_0/S_AXI_CTL] [get_bd_intf_pins smartconnect_0/M01_AXI]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXIS_H2C_0 [get_bd_intf_pins axis_clock_converter_h2c_data/S_AXIS] [get_bd_intf_pins xdma_0/M_AXIS_H2C_0]
|
||||
connect_bd_intf_net -intf_net xdma_0_M_AXI_LITE [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins xdma_0/M_AXI_LITE]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_addr [get_bd_pins gen_xdma_descriptor_c2h/dsc_addr] [get_bd_pins xdma_0/c2h_dsc_byp_dst_addr_0] [get_bd_pins xdma_0/c2h_dsc_byp_src_addr_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_ctl [get_bd_pins gen_xdma_descriptor_c2h/dsc_ctl] [get_bd_pins xdma_0/c2h_dsc_byp_ctl_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_len [get_bd_pins gen_xdma_descriptor_c2h/dsc_len] [get_bd_pins xdma_0/c2h_dsc_byp_len_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_c2h_0_dsc_load [get_bd_pins gen_xdma_descriptor_c2h/dsc_load] [get_bd_pins xdma_0/c2h_dsc_byp_load_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_addr [get_bd_pins gen_xdma_descriptor_h2c/dsc_addr] [get_bd_pins xdma_0/h2c_dsc_byp_dst_addr_0] [get_bd_pins xdma_0/h2c_dsc_byp_src_addr_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_ctl [get_bd_pins gen_xdma_descriptor_h2c/dsc_ctl] [get_bd_pins xdma_0/h2c_dsc_byp_ctl_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_len [get_bd_pins gen_xdma_descriptor_h2c/dsc_len] [get_bd_pins xdma_0/h2c_dsc_byp_len_0]
|
||||
connect_bd_net -net gen_xdma_descriptor_h2c_0_dsc_load [get_bd_pins gen_xdma_descriptor_h2c/dsc_load] [get_bd_pins xdma_0/h2c_dsc_byp_load_0]
|
||||
connect_bd_net -net pcie_clk_buf_inst_IBUF_DS_ODIV2 [get_bd_pins pcie_clk_buf_inst/IBUF_DS_ODIV2] [get_bd_pins xdma_0/sys_clk]
|
||||
connect_bd_net -net pcie_clk_buf_inst_IBUF_OUT [get_bd_pins pcie_clk_buf_inst/IBUF_OUT] [get_bd_pins xdma_0/sys_clk_gt]
|
||||
connect_bd_net -net pcie_perstn_1 [get_bd_pins pcie_perstn] [get_bd_pins xdma_0/sys_rst_n]
|
||||
connect_bd_net -net net_refclk200 [get_bd_pins refclk200] [get_bd_pins axis_clock_converter_c2h_cmd/s_axis_aclk] [get_bd_pins axis_clock_converter_c2h_data/s_axis_aclk] [get_bd_pins axis_clock_converter_h2c_cmd/s_axis_aclk] [get_bd_pins axis_clock_converter_h2c_data/m_axis_aclk]
|
||||
connect_bd_net -net net_refclk200_resetn [get_bd_pins refclk200_resetn] [get_bd_pins axis_clock_converter_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_clock_converter_c2h_data/s_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_data/m_axis_aresetn]
|
||||
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins axi_clk_resetn] [get_bd_pins axi_firewall_0/aresetn] [get_bd_pins axis_clock_converter_c2h_cmd/m_axis_aresetn] [get_bd_pins axis_clock_converter_c2h_data/m_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_cmd/m_axis_aresetn] [get_bd_pins axis_clock_converter_h2c_data/s_axis_aresetn] [get_bd_pins gen_xdma_descriptor_c2h/resetn] [get_bd_pins gen_xdma_descriptor_h2c/resetn] [get_bd_pins smartconnect_0/aresetn]
|
||||
connect_bd_net -net usr_irq_req_1 [get_bd_pins usr_irq_req] [get_bd_pins xdma_0/usr_irq_req]
|
||||
connect_bd_net -net xdma_0_axi_aclk [get_bd_pins axi_aclk] [get_bd_pins axi_firewall_0/aclk] [get_bd_pins axis_clock_converter_c2h_cmd/m_axis_aclk] [get_bd_pins axis_clock_converter_c2h_data/m_axis_aclk] [get_bd_pins axis_clock_converter_h2c_cmd/m_axis_aclk] [get_bd_pins axis_clock_converter_h2c_data/s_axis_aclk] [get_bd_pins gen_xdma_descriptor_c2h/clk] [get_bd_pins gen_xdma_descriptor_h2c/clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins xdma_0/axi_aclk]
|
||||
connect_bd_net -net xdma_0_axi_aresetn [get_bd_pins axi_aresetn] [get_bd_pins xdma_0/axi_aresetn]
|
||||
connect_bd_net -net xdma_0_c2h_dsc_byp_ready_0 [get_bd_pins gen_xdma_descriptor_c2h/dsc_ready] [get_bd_pins xdma_0/c2h_dsc_byp_ready_0]
|
||||
connect_bd_net -net xdma_0_h2c_dsc_byp_ready_0 [get_bd_pins gen_xdma_descriptor_h2c/dsc_ready] [get_bd_pins xdma_0/h2c_dsc_byp_ready_0]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user