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FPGA: increase burst length and latency for internal packet generator AXI interface

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leonarski_f
2023-09-07 05:54:24 +02:00
parent a6377239cf
commit 4032ce09b8
1 changed files with 1 additions and 1 deletions
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fpga/hls/internal_packet_generator.cpp
+1 -1
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@@ -14,7 +14,7 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
#pragma HLS INTERFACE register both axis port=addr_in
#pragma HLS INTERFACE register both axis port=addr_out
#pragma HLS INTERFACE m_axi port=frame bundle=frame depth=512 offset=off \
max_read_burst_length=16 max_write_burst_length=16 latency=2 num_write_outstanding=2 num_read_outstanding=2
max_read_burst_length=64 max_write_burst_length=2 latency=3 num_write_outstanding=2 num_read_outstanding=2
#pragma HLS INTERFACE ap_none register port=in_cancel