From 4032ce09b8030875bb39067b991ef2c707ddd3f9 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Thu, 7 Sep 2023 05:54:24 +0200 Subject: [PATCH] FPGA: increase burst length and latency for internal packet generator AXI interface --- fpga/hls/internal_packet_generator.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/hls/internal_packet_generator.cpp b/fpga/hls/internal_packet_generator.cpp index 2f3df9b5..b3040e5f 100644 --- a/fpga/hls/internal_packet_generator.cpp +++ b/fpga/hls/internal_packet_generator.cpp @@ -14,7 +14,7 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out, #pragma HLS INTERFACE register both axis port=addr_in #pragma HLS INTERFACE register both axis port=addr_out #pragma HLS INTERFACE m_axi port=frame bundle=frame depth=512 offset=off \ - max_read_burst_length=16 max_write_burst_length=16 latency=2 num_write_outstanding=2 num_read_outstanding=2 + max_read_burst_length=64 max_write_burst_length=2 latency=3 num_write_outstanding=2 num_read_outstanding=2 #pragma HLS INTERFACE ap_none register port=in_cancel