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FPGA: Make sure all HBM handles are accessible - scale FIFOs properly

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leonarski_f
2023-09-17 22:31:46 +02:00
parent a94bdacea9
commit a80fd362a6
2 changed files with 3 additions and 2 deletions
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fpga/hls/load_from_hbm.cpp
+1 -1
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@@ -28,7 +28,7 @@ void load_from_hbm(STREAM_512 &data_in,
data_in >> packet;
data_out << packet;
for (ap_uint<16> i = 0; i < hbm_size_bytes / (RAW_MODULE_SIZE * sizeof(uint32_t) / 2); i++)
for (ap_uint<16> i = 0; i < hbm_size_bytes * 4 / (RAW_MODULE_SIZE * sizeof(uint32_t)); i++)
m_axis_free_handles << i;
ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32;
fpga/scripts/jfjoch.tcl
+2 -1
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@@ -141,7 +141,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
# Create instance: axis_compl_fifo_0, and set properties
set axis_compl_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_0 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {16} \
CONFIG.FIFO_DEPTH {2048} \
CONFIG.FIFO_MEMORY_TYPE {ultra} \
] $axis_compl_fifo_0
# Create instance: axis_compl_fifo_1, and set properties