From a80fd362a6d197fd4e9615191aadb7652744222c Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Sun, 17 Sep 2023 22:31:46 +0200 Subject: [PATCH] FPGA: Make sure all HBM handles are accessible - scale FIFOs properly --- fpga/hls/load_from_hbm.cpp | 2 +- fpga/scripts/jfjoch.tcl | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fpga/hls/load_from_hbm.cpp b/fpga/hls/load_from_hbm.cpp index 7e366b1c..d1e824e7 100644 --- a/fpga/hls/load_from_hbm.cpp +++ b/fpga/hls/load_from_hbm.cpp @@ -28,7 +28,7 @@ void load_from_hbm(STREAM_512 &data_in, data_in >> packet; data_out << packet; - for (ap_uint<16> i = 0; i < hbm_size_bytes / (RAW_MODULE_SIZE * sizeof(uint32_t) / 2); i++) + for (ap_uint<16> i = 0; i < hbm_size_bytes * 4 / (RAW_MODULE_SIZE * sizeof(uint32_t)); i++) m_axis_free_handles << i; ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32; diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl index 32e048f3..bc824500 100644 --- a/fpga/scripts/jfjoch.tcl +++ b/fpga/scripts/jfjoch.tcl @@ -141,7 +141,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } { # Create instance: axis_compl_fifo_0, and set properties set axis_compl_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_compl_fifo_0 ] set_property -dict [ list \ - CONFIG.FIFO_DEPTH {16} \ + CONFIG.FIFO_DEPTH {2048} \ + CONFIG.FIFO_MEMORY_TYPE {ultra} \ ] $axis_compl_fifo_0 # Create instance: axis_compl_fifo_1, and set properties