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FPGA: Increase FIFO size to improve buffering capability

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This commit is contained in:
leonarski_f
2023-09-07 12:23:38 +02:00
parent dd002e3d6d
commit 35aa21fefe
2 changed files with 2 additions and 2 deletions
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2
fpga/scripts/jfjoch.tcl
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@@ -186,7 +186,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
# Create instance: axis_data_fifo_5, and set properties
set axis_data_fifo_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_5 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {8192} \
CONFIG.FIFO_DEPTH {32768} \
CONFIG.FIFO_MEMORY_TYPE {ultra} \
CONFIG.HAS_AEMPTY {1} \
CONFIG.HAS_AFULL {1} \

2
fpga/scripts/mac_100g_pcie.tcl
View File

@@ -65,7 +65,7 @@ proc create_hier_cell_mac_100g { parentCell nameHier } {
# Create instance: axis_data_fifo_rx_1, and set properties
set axis_data_fifo_rx_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_1 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {4096} \
CONFIG.FIFO_DEPTH {16384} \
CONFIG.FIFO_MEMORY_TYPE {ultra} \
CONFIG.ENABLE_ECC {1} \
] $axis_data_fifo_rx_1