From 35aa21fefec08ee75f45aaf7bbd1fffe9b0ec08f Mon Sep 17 00:00:00 2001
From: Filip Leonarski <filip.leonarski@psi.ch>
Date: Thu, 7 Sep 2023 12:23:38 +0200
Subject: [PATCH] FPGA: Increase FIFO size to improve buffering capability

---
 fpga/scripts/jfjoch.tcl        | 2 +-
 fpga/scripts/mac_100g_pcie.tcl | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpga/scripts/jfjoch.tcl b/fpga/scripts/jfjoch.tcl
index ba039c77..52ef5551 100644
--- a/fpga/scripts/jfjoch.tcl
+++ b/fpga/scripts/jfjoch.tcl
@@ -186,7 +186,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   # Create instance: axis_data_fifo_5, and set properties
   set axis_data_fifo_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_5 ]
   set_property -dict [ list \
-   CONFIG.FIFO_DEPTH {8192} \
+   CONFIG.FIFO_DEPTH {32768} \
    CONFIG.FIFO_MEMORY_TYPE {ultra} \
    CONFIG.HAS_AEMPTY {1} \
    CONFIG.HAS_AFULL {1} \
diff --git a/fpga/scripts/mac_100g_pcie.tcl b/fpga/scripts/mac_100g_pcie.tcl
index 87785efd..0a157394 100644
--- a/fpga/scripts/mac_100g_pcie.tcl
+++ b/fpga/scripts/mac_100g_pcie.tcl
@@ -65,7 +65,7 @@ proc create_hier_cell_mac_100g { parentCell nameHier } {
   # Create instance: axis_data_fifo_rx_1, and set properties
   set axis_data_fifo_rx_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_rx_1 ]
   set_property -dict [ list \
-   CONFIG.FIFO_DEPTH {4096} \
+   CONFIG.FIFO_DEPTH {16384} \
    CONFIG.FIFO_MEMORY_TYPE {ultra} \
    CONFIG.ENABLE_ECC {1} \
  ] $axis_data_fifo_rx_1