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FPGA: Use datamover for save_to_hbm and load_from_hbm

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This commit is contained in:
leonarski_f
2023-09-19 07:36:56 +02:00
parent 98877e5bb3
commit 86123eb2fe
7 changed files with 184 additions and 32 deletions
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fpga/hls/hls_jfjoch.h
+9 -5
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@@ -145,8 +145,10 @@ void load_from_hbm(STREAM_512 &data_in,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16> > &m_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
hls::stream<ap_axiu<256,1,1,1> > &hbm_in_0,
hls::stream<ap_axiu<256,1,1,1> > &hbm_in_1,
hls::stream<axis_datamover_ctrl> &datamover_0_cmd,
hls::stream<axis_datamover_ctrl> &datamover_1_cmd,
ap_uint<32> hbm_size_bytes);
void save_to_hbm(STREAM_512 &data_in,
@@ -154,9 +156,11 @@ void save_to_hbm(STREAM_512 &data_in,
hls::stream<axis_addr> &addr_in,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16>> &s_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<32> hbm_size_bytes) ;
hls::stream<ap_axiu<256,1,1,1> > &hbm_out_0,
hls::stream<ap_axiu<256,1,1,1> > &hbm_out_1,
hls::stream<axis_datamover_ctrl> &datamover_0_cmd,
hls::stream<axis_datamover_ctrl> &datamover_1_cmd,
ap_uint<32> hbm_size_bytes);
void mask_missing(STREAM_512 &data_in,
STREAM_512 &data_out,
fpga/hls/load_from_hbm.cpp
+20 -9
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@@ -8,8 +8,10 @@ void load_from_hbm(STREAM_512 &data_in,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16> > &m_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
hls::stream<ap_axiu<256,1,1,1> > &hbm_in_0,
hls::stream<ap_axiu<256,1,1,1> > &hbm_in_1,
hls::stream<axis_datamover_ctrl> &datamover_0_cmd,
hls::stream<axis_datamover_ctrl> &datamover_1_cmd,
ap_uint<32> hbm_size_bytes) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
@@ -17,12 +19,12 @@ void load_from_hbm(STREAM_512 &data_in,
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_completion
#pragma HLS INTERFACE register both axis port=m_axis_free_handles
#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
#pragma HLS INTERFACE register both axis port=hbm_in_0
#pragma HLS INTERFACE register both axis port=hbm_in_1
#pragma HLS INTERFACE register both axis port=datamover_0_cmd
#pragma HLS INTERFACE register both axis port=datamover_1_cmd
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
packet_512_t packet;
data_in >> packet;
@@ -41,11 +43,20 @@ void load_from_hbm(STREAM_512 &data_in,
size_t offset = ((cmpl.handle / 2) * RAW_MODULE_SIZE * sizeof(uint16_t)) / 64;
if (cmpl.handle % 2 == 1)
offset += hbm_size_bytes / 32;
setup_datamover(datamover_0_cmd, (offset_hbm_0 + offset) * 32, RAW_MODULE_SIZE * sizeof(uint16_t) / 2);
setup_datamover(datamover_1_cmd, (offset_hbm_1 + offset) * 32, RAW_MODULE_SIZE * sizeof(uint16_t) / 2);
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
ap_axiu<256,1,1,1> packet_in_0;
ap_axiu<256,1,1,1> packet_in_1;
hbm_in_0 >> packet_in_0;
hbm_in_1 >> packet_in_1;
packet_512_t packet_out;
packet_out.data(255, 0) = d_hbm_p0[offset_hbm_0 + offset + i];
packet_out.data(511, 256) = d_hbm_p1[offset_hbm_1 + offset + i];
packet_out.data(255, 0) = packet_in_0.data;
packet_out.data(511, 256) = packet_in_1.data;
packet_out.last = (i == RAW_MODULE_SIZE * sizeof(uint16_t) / 64 - 1);
packet_out.id = 0;
packet_out.dest = 0;
fpga/hls/save_to_hbm.cpp
+25 -9
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@@ -8,8 +8,10 @@ void save_to_hbm(STREAM_512 &data_in,
hls::stream<axis_addr> &addr_in,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16>> &s_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
hls::stream<ap_axiu<256,1,1,1> > &hbm_out_0,
hls::stream<ap_axiu<256,1,1,1> > &hbm_out_1,
hls::stream<axis_datamover_ctrl> &datamover_0_cmd,
hls::stream<axis_datamover_ctrl> &datamover_1_cmd,
ap_uint<32> hbm_size_bytes) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
@@ -17,13 +19,12 @@ void save_to_hbm(STREAM_512 &data_in,
#pragma HLS INTERFACE register both axis port=addr_in
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_free_handles
#pragma HLS INTERFACE register both axis port=hbm_out_0
#pragma HLS INTERFACE register both axis port=hbm_out_1
#pragma HLS INTERFACE register both axis port=datamover_0_cmd
#pragma HLS INTERFACE register both axis port=datamover_1_cmd
#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
axis_completion cmpl[MAX_MODULES_FPGA*2];
for (int i = 0; i < MAX_MODULES_FPGA*2; i++) {
@@ -80,10 +81,25 @@ void save_to_hbm(STREAM_512 &data_in,
if (cmpl[id].handle % 2 == 1)
offset += hbm_size_bytes / 32;
setup_datamover(datamover_0_cmd, (offset_hbm_0 + offset) * 32, 4096);
setup_datamover(datamover_1_cmd, (offset_hbm_1 + offset) * 32, 4096);
for (int i = 0; i < 128; i++) {
data_in >> packet_in;
d_hbm_p0[offset_hbm_0 + offset + i] = packet_in.data(255, 0);
d_hbm_p1[offset_hbm_1 + offset + i] = packet_in.data(511, 256);
ap_axiu<256,1,1,1> packet_out;
packet_out.keep = UINT32_MAX;
packet_out.strb = UINT32_MAX;
packet_out.user = 0;
packet_out.dest = 0;
packet_out.id = 0;
packet_out.last = (i == 127);
packet_out.data = packet_in.data(255, 0);
hbm_out_0 << packet_out;
packet_out.data = packet_in.data(511, 256);
hbm_out_1 << packet_out;
}
addr_in >> addr;
fpga/scripts/bd_pcie.tcl
+1
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@@ -143,6 +143,7 @@ xilinx.com:ip:axi_protocol_converter:2.1\
xilinx.com:ip:axi_register_slice:2.1\
xilinx.com:ip:hbm:1.0\
xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:axi_datamover:5.1\
xilinx.com:ip:axis_data_fifo:2.0\
xilinx.com:ip:axis_register_slice:1.1\
psi.ch:hls:data_collection_fsm:1.0\
fpga/scripts/jfjoch.tcl
+111 -7
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@@ -120,6 +120,44 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.SINGLE_PORT_BRAM {1} \
] $axi_bram_ctrl_internal_packet_generator_1
# Create instance: axi_datamover_0, and set properties
set axi_datamover_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_0 ]
set_property -dict [ list \
CONFIG.c_addr_width {64} \
CONFIG.c_dummy {1} \
CONFIG.c_enable_mm2s {1} \
CONFIG.c_include_mm2s {Full} \
CONFIG.c_include_mm2s_stsfifo {true} \
CONFIG.c_m_axi_mm2s_data_width {256} \
CONFIG.c_m_axi_mm2s_id_width {6} \
CONFIG.c_m_axi_s2mm_id_width {6} \
CONFIG.c_m_axis_mm2s_tdata_width {256} \
CONFIG.c_mm2s_btt_used {23} \
CONFIG.c_mm2s_burst_size {16} \
CONFIG.c_mm2s_include_sf {true} \
CONFIG.c_s2mm_btt_used {23} \
CONFIG.c_single_interface {1} \
] $axi_datamover_0
# Create instance: axi_datamover_1, and set properties
set axi_datamover_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_1 ]
set_property -dict [ list \
CONFIG.c_addr_width {64} \
CONFIG.c_dummy {1} \
CONFIG.c_enable_mm2s {1} \
CONFIG.c_include_mm2s {Full} \
CONFIG.c_include_mm2s_stsfifo {true} \
CONFIG.c_m_axi_mm2s_data_width {256} \
CONFIG.c_m_axi_mm2s_id_width {6} \
CONFIG.c_m_axi_s2mm_id_width {6} \
CONFIG.c_m_axis_mm2s_tdata_width {256} \
CONFIG.c_mm2s_btt_used {23} \
CONFIG.c_mm2s_burst_size {16} \
CONFIG.c_mm2s_include_sf {true} \
CONFIG.c_s2mm_btt_used {23} \
CONFIG.c_single_interface {1} \
] $axi_datamover_1
# Create instance: axis_addr_fifo_0, and set properties
set axis_addr_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_0 ]
set_property -dict [ list \
@@ -245,6 +283,54 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.TDATA_NUM_BYTES {64} \
] $axis_data_fifo_h2c_data
# Create instance: axis_datamover_cmd_fifo_0, and set properties
set axis_datamover_cmd_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_cmd_fifo_0 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {16} \
] $axis_datamover_cmd_fifo_0
# Create instance: axis_datamover_cmd_fifo_1, and set properties
set axis_datamover_cmd_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_cmd_fifo_1 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {16} \
] $axis_datamover_cmd_fifo_1
# Create instance: axis_datamover_cmd_fifo_2, and set properties
set axis_datamover_cmd_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_cmd_fifo_2 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {16} \
] $axis_datamover_cmd_fifo_2
# Create instance: axis_datamover_cmd_fifo_3, and set properties
set axis_datamover_cmd_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_cmd_fifo_3 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {16} \
] $axis_datamover_cmd_fifo_3
# Create instance: axis_datamover_fifo_0, and set properties
set axis_datamover_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_fifo_0 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {2048} \
] $axis_datamover_fifo_0
# Create instance: axis_datamover_fifo_1, and set properties
set axis_datamover_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_fifo_1 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {2048} \
] $axis_datamover_fifo_1
# Create instance: axis_datamover_fifo_2, and set properties
set axis_datamover_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_fifo_2 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {2048} \
] $axis_datamover_fifo_2
# Create instance: axis_datamover_fifo_3, and set properties
set axis_datamover_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_datamover_fifo_3 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {2048} \
] $axis_datamover_fifo_3
# Create instance: axis_eth_in_fifo, and set properties
set axis_eth_in_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_eth_in_fifo ]
set_property -dict [ list \
@@ -397,6 +483,9 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
# Create instance: network_stack
create_hier_cell_network_stack $hier_obj network_stack
# Create instance: one, and set properties
set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ]
# Create instance: save_to_hbm_0, and set properties
set save_to_hbm_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:save_to_hbm:1.0 save_to_hbm_0 ]
@@ -428,6 +517,10 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS]
connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_1_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_1/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTB]
connect_bd_intf_net -intf_net axi_bram_ctrl_internal_packet_generator_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_internal_packet_generator_0/BRAM_PORTA] [get_bd_intf_pins internal_packet_generator_uram/BRAM_PORTA]
connect_bd_intf_net -intf_net axi_datamover_0_M_AXI [get_bd_intf_pins m_axi_d_hbm_p12] [get_bd_intf_pins axi_datamover_0/M_AXI]
connect_bd_intf_net -intf_net axi_datamover_0_M_AXIS_MM2S [get_bd_intf_pins axi_datamover_0/M_AXIS_MM2S] [get_bd_intf_pins axis_datamover_fifo_2/S_AXIS]
connect_bd_intf_net -intf_net axi_datamover_1_M_AXI [get_bd_intf_pins m_axi_d_hbm_p14] [get_bd_intf_pins axi_datamover_1/M_AXI]
connect_bd_intf_net -intf_net axi_datamover_1_M_AXIS_MM2S [get_bd_intf_pins axi_datamover_1/M_AXIS_MM2S] [get_bd_intf_pins axis_datamover_fifo_3/S_AXIS]
connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins axis_register_slice_1/S_AXIS]
connect_bd_intf_net -intf_net axis_addr_fifo_1_M_AXIS [get_bd_intf_pins axis_addr_fifo_1/M_AXIS] [get_bd_intf_pins axis_register_slice_2/S_AXIS]
connect_bd_intf_net -intf_net axis_compl_fifo_0_M_AXIS [get_bd_intf_pins axis_compl_fifo_0/M_AXIS] [get_bd_intf_pins load_from_hbm_0/s_axis_completion]
@@ -444,6 +537,14 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net axis_data_fifo_c2h_data_M_AXIS [get_bd_intf_pins m_axis_c2h_data] [get_bd_intf_pins axis_data_fifo_c2h_data/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_h2c_cmd_M_AXIS [get_bd_intf_pins m_axis_h2c_datamover_cmd] [get_bd_intf_pins axis_data_fifo_h2c_cmd/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_h2c_data_M_AXIS [get_bd_intf_pins axis_data_fifo_h2c_data/M_AXIS] [get_bd_intf_pins axis_register_slice_data_in_0/S_AXIS]
connect_bd_intf_net -intf_net axis_datamover_cmd_fifo_2_M_AXIS [get_bd_intf_pins axi_datamover_0/S_AXIS_MM2S_CMD] [get_bd_intf_pins axis_datamover_cmd_fifo_2/M_AXIS]
connect_bd_intf_net -intf_net axis_datamover_cmd_fifo_3_M_AXIS [get_bd_intf_pins axi_datamover_1/S_AXIS_MM2S_CMD] [get_bd_intf_pins axis_datamover_cmd_fifo_3/M_AXIS]
connect_bd_intf_net -intf_net axis_datamover_fifo_0_M_AXIS [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM] [get_bd_intf_pins axis_datamover_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net axis_datamover_fifo_1_M_AXIS [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM_CMD] [get_bd_intf_pins axis_datamover_cmd_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net axis_datamover_fifo_2_M_AXIS [get_bd_intf_pins axi_datamover_1/S_AXIS_S2MM] [get_bd_intf_pins axis_datamover_fifo_1/M_AXIS]
connect_bd_intf_net -intf_net axis_datamover_fifo_2_M_AXIS1 [get_bd_intf_pins axis_datamover_fifo_2/M_AXIS] [get_bd_intf_pins load_from_hbm_0/hbm_in_0]
connect_bd_intf_net -intf_net axis_datamover_fifo_3_M_AXIS [get_bd_intf_pins axi_datamover_1/S_AXIS_S2MM_CMD] [get_bd_intf_pins axis_datamover_cmd_fifo_1/M_AXIS]
connect_bd_intf_net -intf_net axis_datamover_fifo_3_M_AXIS1 [get_bd_intf_pins axis_datamover_fifo_3/M_AXIS] [get_bd_intf_pins load_from_hbm_0/hbm_in_1]
connect_bd_intf_net -intf_net axis_eth_in_fifo_M_AXIS [get_bd_intf_pins axis_eth_in_fifo/M_AXIS] [get_bd_intf_pins network_stack/eth_in]
connect_bd_intf_net -intf_net axis_frame_generator_fifo_0_M_AXIS [get_bd_intf_pins axis_frame_generator_fifo_0/M_AXIS] [get_bd_intf_pins stream_merge_0/input_0]
connect_bd_intf_net -intf_net axis_hbm_handles_fifo_M_AXIS [get_bd_intf_pins axis_hbm_handles_fifo/M_AXIS] [get_bd_intf_pins save_to_hbm_0/s_axis_free_handles]
@@ -484,8 +585,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p0 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S01_AXI]
connect_bd_intf_net -intf_net load_calibration_0_m_axi_d_hbm_p1 [get_bd_intf_pins load_calibration_0/m_axi_d_hbm_p1] [get_bd_intf_pins smartconnect_2/S01_AXI]
connect_bd_intf_net -intf_net load_from_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins load_from_hbm_0/data_out]
connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p12] [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p0]
connect_bd_intf_net -intf_net load_from_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p14] [get_bd_intf_pins load_from_hbm_0/m_axi_d_hbm_p1]
connect_bd_intf_net -intf_net load_from_hbm_0_datamover_0_cmd [get_bd_intf_pins axis_datamover_cmd_fifo_2/S_AXIS] [get_bd_intf_pins load_from_hbm_0/datamover_0_cmd]
connect_bd_intf_net -intf_net load_from_hbm_0_datamover_1_cmd [get_bd_intf_pins axis_datamover_cmd_fifo_3/S_AXIS] [get_bd_intf_pins load_from_hbm_0/datamover_1_cmd]
connect_bd_intf_net -intf_net load_from_hbm_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_1/S_AXIS] [get_bd_intf_pins load_from_hbm_0/m_axis_completion]
connect_bd_intf_net -intf_net load_from_hbm_0_m_axis_free_handles [get_bd_intf_pins axis_hbm_handles_fifo/S_AXIS] [get_bd_intf_pins load_from_hbm_0/m_axis_free_handles]
connect_bd_intf_net -intf_net mailbox_0_M1_AXIS [get_bd_intf_pins axis_work_request_fifo_0/S_AXIS] [get_bd_intf_pins mailbox_0/M1_AXIS]
@@ -495,8 +596,10 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net network_stack_udp_out [get_bd_intf_pins axis_udp_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_out]
connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins smartconnect_0/S00_AXI]
connect_bd_intf_net -intf_net save_to_hbm_0_data_out [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins save_to_hbm_0/data_out]
connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p13] [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p0]
connect_bd_intf_net -intf_net save_to_hbm_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p15] [get_bd_intf_pins save_to_hbm_0/m_axi_d_hbm_p1]
connect_bd_intf_net -intf_net save_to_hbm_0_datamover_0_cmd [get_bd_intf_pins axis_datamover_cmd_fifo_0/S_AXIS] [get_bd_intf_pins save_to_hbm_0/datamover_0_cmd]
connect_bd_intf_net -intf_net save_to_hbm_0_datamover_1_cmd [get_bd_intf_pins axis_datamover_cmd_fifo_1/S_AXIS] [get_bd_intf_pins save_to_hbm_0/datamover_1_cmd]
connect_bd_intf_net -intf_net save_to_hbm_0_hbm_out_0 [get_bd_intf_pins axis_datamover_fifo_0/S_AXIS] [get_bd_intf_pins save_to_hbm_0/hbm_out_0]
connect_bd_intf_net -intf_net save_to_hbm_0_hbm_out_1 [get_bd_intf_pins axis_datamover_fifo_1/S_AXIS] [get_bd_intf_pins save_to_hbm_0/hbm_out_1]
connect_bd_intf_net -intf_net save_to_hbm_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_0/S_AXIS] [get_bd_intf_pins save_to_hbm_0/m_axis_completion]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins action_config_0/s_axi] [get_bd_intf_pins smartconnect_0/M00_AXI]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins mailbox_0/S0_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
@@ -521,7 +624,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules]
connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells]
connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy]
connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aclk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_addr_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_2/aclk] [get_bd_pins axis_register_slice_3/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
connect_bd_net -net axis_addr_fifo_0_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_0/almost_empty]
connect_bd_net -net axis_addr_fifo_0_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_0/almost_full]
connect_bd_net -net axis_addr_fifo_4_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_addr_fifo_1/almost_empty]
@@ -572,8 +675,9 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net network_stack_packets_sls_ap_vld [get_bd_pins action_config_0/packets_sls_valid] [get_bd_pins network_stack/packets_sls_ap_vld]
connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp]
connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld]
connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
connect_bd_net -net one_dout [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins one/dout]
connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_addr_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_3/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_2/aresetn] [get_bd_pins axis_register_slice_3/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins axi_bram_ctrl_internal_packet_generator_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_internal_packet_generator_1/s_axi_aresetn] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter]
connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld]
connect_bd_net -net timer_host_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host/counter]
receiver/HLSSimulatedDevice.cpp
+13 -2
View File
@@ -31,6 +31,10 @@ HLSSimulatedDevice::HLSSimulatedDevice(uint16_t data_stream, size_t in_frame_buf
: FPGAAcquisitionDevice(data_stream),
datamover_in(Direction::Input),
datamover_out(Direction::Output, nullptr, 256),
datamover_out_hbm_0(Direction::Output, (char *) hbm.data(), 16),
datamover_out_hbm_1(Direction::Output, (char *) hbm.data(), 16),
datamover_in_hbm_0(Direction::Input, (char *) hbm.data()),
datamover_in_hbm_1(Direction::Input, (char *) hbm.data()),
idle(true), hbm(hbm_if_size / 32 * hbm_if_count) {
mac_addr = 0xCCAA11223344;
ipv4_addr = 0x0132010A;
@@ -311,8 +315,15 @@ void HLSSimulatedDevice::HLSMainThread() {
hls::stream<ap_uint<16>> handles;
// 3. Cache images in HBM
hls_cores.emplace_back([&] { save_to_hbm(converted_0, converted_1, addr2, compl0, handles, hbm.data(), hbm.data(), hbm_if_size);});
hls_cores.emplace_back([&] { load_from_hbm(converted_1, converted_2, compl0, compl1, handles, hbm.data(), hbm.data(), hbm_if_size);});
hls_cores.emplace_back([&] { save_to_hbm(converted_0, converted_1, addr2, compl0, handles,
datamover_out_hbm_0.GetDataStream(), datamover_out_hbm_1.GetDataStream(),
datamover_out_hbm_0.GetCtrlStream(), datamover_out_hbm_1.GetCtrlStream(),
hbm_if_size);});
hls_cores.emplace_back([&] { load_from_hbm(converted_1, converted_2, compl0, compl1, handles,
datamover_in_hbm_0.GetDataStream(), datamover_in_hbm_1.GetDataStream(),
datamover_in_hbm_0.GetCtrlStream(), datamover_in_hbm_1.GetCtrlStream(),
hbm_if_size);});
// 4. Mask missing pixels
hls_cores.emplace_back([&] { mask_missing(converted_2, converted_3, compl1, compl2);});
receiver/HLSSimulatedDevice.h
+5
View File
@@ -32,6 +32,11 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice {
Datamover<512> datamover_in;
Datamover<512> datamover_out;
Datamover<256> datamover_in_hbm_0;
Datamover<256> datamover_in_hbm_1;
Datamover<256> datamover_out_hbm_0;
Datamover<256> datamover_out_hbm_1;
ap_uint<1> run_data_collection;
ap_uint<1> cancel_data_collection;
volatile ap_uint<1> host_writer_idle;