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Code Issues Pull Requests Actions 1 Packages Projects Releases 37 Wiki Activity
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dd002e3d6dfee91f4fb53e79a0d421b772896ad0
Jungfraujoch/fpga/scripts
History
Filip Leonarski dd002e3d6d FPGA: Build only 100G solution (no bifurcated design)
2023-09-07 12:10:38 +02:00
..
bd_pcie.tcl
FPGA: Build only 100G solution (no bifurcated design)
2023-09-07 12:10:38 +02:00
build_pcie_design.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
check_hls.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
hbm_u55c.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
jfjoch.tcl
FPGA: use full AXI for internal packet generator
2023-09-06 18:16:44 +02:00
mac_100g_pcie.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
network_stack.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
pcie_dma.tcl
FPGA: Build only 100G solution (no bifurcated design)
2023-09-07 12:10:38 +02:00
setup_action.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
snap_env.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
synth_and_impl.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
synth_hls_function.tcl
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
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