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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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6e85a30930
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FPGA: Change FIFO size to improve placing
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2024-01-28 20:11:39 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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07fd769102
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Remove AN/LT capability
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2023-12-18 12:33:31 +01:00 |
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d66b6b949d
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Fix spot finding + fix FPGA network LEDs behavior
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2023-12-16 09:20:46 +01:00 |
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d82bd13917
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Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
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2023-12-14 22:39:17 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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1d3d8d081e
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FPGA: add power report after routing
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2023-11-28 21:30:40 +01:00 |
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657cf802eb
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FPGA: frame_summation_reorder_compl doesn't need ap_start
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2023-11-23 16:39:48 +01:00 |
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a7c2849a84
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FPGA: measure pipeline beats in timer
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2023-11-21 15:55:23 +01:00 |
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39ca47aea9
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FPGA: Add processing stalls
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2023-11-21 15:42:26 +01:00 |
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ba70aa1915
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FPGA: Load calibration issues datamover commands first
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2023-11-18 22:44:37 +01:00 |
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e5397e68cf
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FPGA: Clean-up of HDL modules
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2023-11-18 19:18:26 +01:00 |
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b69d9cb477
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FPGA: Fix setup_action.sh
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2023-11-17 16:48:27 +01:00 |
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c66c06e8f5
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FPGA: Fix setup action
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2023-11-02 15:09:04 +01:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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4fbd747341
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FPGA: Remove multipixel from the pipeline
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2023-10-27 20:47:44 +02:00 |
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4978149fdd
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FPGA: Add register slice in the data pipeline
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2023-10-27 19:43:40 +02:00 |
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c896ec5659
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FPGA: Remove bitshuffle from the pipeline
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2023-10-27 19:41:02 +02:00 |
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f46a8e47a0
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FPGA: Use AggressiveExplore for routing
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2023-10-27 19:12:27 +02:00 |
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08c2427fc7
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FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign
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2023-10-27 15:42:24 +02:00 |
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4fbac629d6
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HLS: Use U55C part number for proper usage statistics
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2023-10-27 13:54:35 +02:00 |
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cf69aef472
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FPGA: Add extra register slices for upside_down
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2023-10-26 22:36:08 +02:00 |
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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6bcf54f603
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FPGA: Add bitshuffle to the design (warning! no test for full integration!)
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2023-10-25 11:07:21 +02:00 |
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d408b3ed2a
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FPGA: Integrate add multipixel into the design
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2023-10-24 18:58:59 +02:00 |
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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f04f7a274b
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FPGA: Name spot finder signals in consistent manner
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2023-10-19 20:52:09 +02:00 |
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c7b7abb34d
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FPGA: Remove register slice for strong pixel result
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2023-10-19 12:14:17 +02:00 |
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6f9f918ee6
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HLS: Improve make scripts, so HLS test bench can be defined
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2023-10-18 16:32:31 +02:00 |
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79df7cf7d5
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FPGA: Add extra AXI-Stream register slices
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2023-10-17 19:40:55 +02:00 |
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c5ca10792e
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FPGA: Clean-up of spot_finder core + update README.MD
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2023-10-16 15:13:47 +02:00 |
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7889f1666a
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FPGA: Spot finder 2nd version improved
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2023-10-04 12:12:43 +02:00 |
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c6afbebd13
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FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result)
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2023-10-02 22:34:49 +02:00 |
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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5bb92aed61
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FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer
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2023-09-29 14:44:08 +02:00 |
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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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027b3aa943
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Revert "FPGA: add register slices"
This reverts commit cf2163a402.
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2023-09-25 21:52:54 +02:00 |
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cf2163a402
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FPGA: add register slices
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2023-09-24 20:28:35 +02:00 |
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df0b0d8b96
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FPGA: add spot finder to the design
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2023-09-24 19:04:58 +02:00 |
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ae6e036628
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FPGA: increase frame_generator memory to 8 MiB
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2023-09-24 14:39:46 +02:00 |
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a70e3cf444
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FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis
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2023-09-22 21:49:41 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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4d482e308a
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FPGA: Fix datamover script
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2023-09-19 07:36:56 +02:00 |
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