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549cc6a8876162ede777ceba9e147fd523bd90d8
Jungfraujoch/fpga/scripts
History
Filip Leonarski 549cc6a887 FPGA: Add ADU histogram (work in progress; needs test)
2023-09-29 16:55:37 +02:00
..
bd_pcie.tcl
FPGA: Add ADU histogram (work in progress; needs test)
2023-09-29 16:55:37 +02:00
build_pcie_design.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
check_hls.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
hbm_u55c.tcl
FPGA: frame generator reads from HBM (work in progress)
2023-09-26 13:14:43 +02:00
jfjoch.tcl
FPGA: Add ADU histogram (work in progress; needs test)
2023-09-29 16:55:37 +02:00
mac_100g_pcie.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
network_stack.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
pcie_dma.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
setup_action.sh
FPGA: Split receiver and FPGA design directories
2023-06-07 21:21:22 +02:00
synth_and_impl.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
synth_hls_function.tcl
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
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