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FPGA: Use AggressiveExplore for routing

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leonarski_f
2023-10-27 19:12:27 +02:00
parent 817d541fb0
commit f46a8e47a0
1 changed files with 2 additions and 2 deletions
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fpga/scripts/synth_and_impl.tcl
+2 -2
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@@ -60,9 +60,9 @@ set WNSPLACE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setu
puts " ***** Place WNS: $WNSPLACE ps *****"
write_checkpoint -force jungfraujoch_place.dcp
if {$WNSPLACE > -1.000} {
if {$WNSPLACE > -0.3000} {
puts "Route design..."
route_design -directive Explore -tns_cleanup -ultrathreads > route_design.log
route_design -directive AggressiveExplore -tns_cleanup -ultrathreads > route_design.log
set WNSROUTE [ get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup] ]
puts "Route WNS (before optimization): $WNSROUTE ps"