FPGA: frame_summation_reorder_compl doesn't need ap_start
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@@ -6,6 +6,7 @@ void frame_summation_reorder_compl(STREAM_512 &data_in,
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STREAM_512 &data_out,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<axis_completion > &m_axis_completion) {
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE axis register both port=data_in
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#pragma HLS INTERFACE axis register both port=data_out
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#pragma HLS INTERFACE axis register both port=s_axis_completion
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@@ -250,7 +250,7 @@ proc create_hier_cell_hbm_cache { parentCell nameHier } {
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connect_bd_net -net axis_hbm_handles_fifo_almost_empty [get_bd_pins hbm_handle_fifo_empty] [get_bd_pins axis_hbm_handles_fifo/almost_empty]
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connect_bd_net -net axis_hbm_handles_fifo_almost_full [get_bd_pins hbm_handle_fifo_full] [get_bd_pins axis_hbm_handles_fifo/almost_full]
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connect_bd_net -net hbm_size_bytes_1 [get_bd_pins hbm_size_bytes] [get_bd_pins load_from_hbm_0/hbm_size_bytes] [get_bd_pins save_to_hbm_0/hbm_size_bytes]
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connect_bd_net -net m_axis_s2mm_sts_tready_1 [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins frame_summation_reor_0/ap_start] [get_bd_pins one/dout]
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connect_bd_net -net m_axis_s2mm_sts_tready_1 [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins one/dout]
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# Restore current instance
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current_bd_instance $oldCurInst
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