FPGA: Add option to invert modules upside down

common/Definitions.h

@@ -54,6 +54,7 @@
 #define MODE_CONV                    0x0001L
 #define MODE_BITSHUFFLE_FPGA         0x0002L
 #define MODE_ADD_MULTIPIXEL          0x0004L
+#define MODE_MODULE_UPSIDE_DOWN      0x0008L
 
 #define TASK_NO_DATA_STREAM UINT16_MAX
 

fpga/hls/CMakeLists.txt

@@ -23,7 +23,8 @@ ADD_LIBRARY( HLSSimulation STATIC
         adu_histo.cpp
         axis_helpers.cpp
         hls_bitshuffle.cpp
-        add_multipixel.cpp)
+        add_multipixel.cpp
+        module_upside_down.cpp)
 
 TARGET_INCLUDE_DIRECTORIES(HLSSimulation PUBLIC ../include)
 TARGET_LINK_LIBRARIES(HLSSimulation CommonFunctions)
@@ -70,6 +71,7 @@ MAKE_HLS_MODULE(axis_128_to_512 axis_helpers.cpp "")
 MAKE_HLS_MODULE(axis_32_to_512 axis_helpers.cpp "")
 MAKE_HLS_MODULE(adu_histo adu_histo.cpp "")
 MAKE_HLS_MODULE(add_multipixel add_multipixel.cpp add_multipixel_tb.cpp)
+MAKE_HLS_MODULE(module_upside_down module_upside_down.cpp module_upside_down_tb.cpp)
 
 SET (HLS_IPS ${HLS_IPS} PARENT_SCOPE)
 ADD_CUSTOM_TARGET(hls DEPENDS ${HLS_IPS})

fpga/hls/hls_jfjoch.h

@@ -329,5 +329,6 @@ void load_calibration(ap_uint<256> *d_hbm_p0,
                       uint64_t in_mem_location[(3 * 16 + 3) * MAX_MODULES_FPGA]) ;
 
 void add_multipixel(STREAM_512 &data_in, STREAM_512 &data_out);
+void module_upside_down(STREAM_512 &data_in, STREAM_512 &data_out);
 
 #endif

fpga/hls/module_upside_down.cpp

@@ -0,0 +1,74 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#include "hls_jfjoch.h"
+
+#define upside(x) ((RAW_MODULE_LINES - 1 - i / 32) * 32 + i % 32)
+
+void module_upside_down(STREAM_512 &data_in, STREAM_512 &data_out) {
+#pragma HLS INTERFACE axis register both port=data_in
+#pragma HLS INTERFACE axis register both port=data_out
+
+    ap_uint<512> memory_0[16384];
+#pragma HLS BIND_STORAGE variable=memory_0 type=ram_t2p impl=uram latency=3
+    ap_uint<512> memory_1[16384];
+#pragma HLS BIND_STORAGE variable=memory_1 type=ram_t2p impl=uram latency=3
+
+    ap_uint<1> mem_0_full = 0;
+    ap_uint<1> mem_1_full = 0;
+    ap_uint<1> curr_mem = 0;
+
+    packet_512_t packet_in, packet_out;
+    data_in >> packet_in;
+    ap_uint<1> reverse = ((ACT_REG_MODE(packet_in.data) & MODE_MODULE_UPSIDE_DOWN)) ? 1 : 0;
+    data_out << packet_in;
+
+    data_in >> packet_in;
+    if (reverse) {
+        while (!packet_in.user) {
+            if (curr_mem == 0) {
+                for (int i = 0; i < 16384; i++) {
+#pragma HLS PIPELINE II=1
+                    memory_0[i] = packet_in.data;
+                    if (mem_1_full) {
+                        packet_out.data = memory_1[upside(i)];
+                        data_out << packet_out;
+                    }
+                    data_in >> packet_in;
+                }
+                mem_0_full = 1;
+                mem_1_full = 0;
+                curr_mem = 1;
+            } else {
+                for (int i = 0; i < 16384; i++) {
+#pragma HLS PIPELINE II=1
+                    memory_1[i] = packet_in.data;
+                    if (mem_0_full) {
+                        packet_out.data = memory_0[upside(i)];
+                        data_out << packet_out;
+                    }
+                    data_in >> packet_in;
+                }
+                mem_0_full = 0;
+                mem_1_full = 1;
+                curr_mem = 0;
+            }
+        }
+        drain_memory:
+        for (int i = 0; i < 16384; i++) {
+#pragma HLS PIPELINE II=1
+            if (mem_0_full)
+                packet_out.data = memory_0[upside(i)];
+            else
+                packet_out.data = memory_1[upside(i)];
+            data_out << packet_out;
+        }
+
+    } else {
+        while (!packet_in.user) {
+#pragma HLS PIPELINE II=1
+            data_out << packet_in;
+            data_in >> packet_in;
+        }
+    }
+    data_out << packet_in;
+}

fpga/hls/module_upside_down_tb.cpp

@@ -0,0 +1,71 @@
+// Copyright (2019-2023) Paul Scherrer Institute
+
+#include <random>
+
+#include "hls_jfjoch.h"
+
+int main() {
+
+    int ret = 0;
+
+    STREAM_512 input;
+    STREAM_512 output;
+
+    for (size_t nframes = 1; nframes < 5; nframes++) {
+        std::vector<int16_t> input_frame(nframes * RAW_MODULE_SIZE);
+        std::vector<int16_t> input_frame_transformed(nframes * RAW_MODULE_SIZE);
+        std::vector<int16_t> output_frame(nframes * RAW_MODULE_SIZE);
+
+        std::mt19937 g1(1387);
+        std::uniform_int_distribution<uint16_t> dist(0, 65535);
+
+        for (int n = 0; n < nframes; n++) {
+            for (int line = 0; line < RAW_MODULE_LINES; line++) {
+                size_t line_transformed = RAW_MODULE_LINES - 1 - line;
+                for (int col = 0; col < RAW_MODULE_COLS; col++) {
+                    uint16_t tmp = dist(g1);
+                    input_frame[n * RAW_MODULE_SIZE + line * RAW_MODULE_COLS + col] = tmp;
+                    input_frame_transformed[n * RAW_MODULE_SIZE + line_transformed * RAW_MODULE_COLS + col] = tmp;
+                }
+            }
+        }
+
+        auto input_frame_512 = (ap_uint<512>*) input_frame.data();
+        auto output_frame_512 = (ap_uint<512>*) output_frame.data();
+
+        ap_uint<512> action_control = 0;
+        ACT_REG_MODE(action_control) = MODE_MODULE_UPSIDE_DOWN;
+
+        input << packet_512_t { .data = action_control, .user = 0 };
+        for (int i = 0; i < nframes * RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++)
+            input << packet_512_t { .data = input_frame_512[i], .user = 0 };
+
+        input << packet_512_t { .user = 1 };
+
+        module_upside_down(input, output);
+
+        if (input.size() != 0)
+            ret = 1;
+
+        if (output.size() != nframes * RAW_MODULE_SIZE * sizeof(uint16_t) / 64 + 2)
+            ret = 1;
+
+        output.read();
+        for (int i = 0; i < nframes * RAW_MODULE_SIZE * sizeof(uint16_t) / 64 ; i++)
+            output_frame_512[i] = output.read().data;
+        output.read();
+
+        if (output_frame != input_frame_transformed) {
+            std::cout << "Input and output don't match" << std::endl;
+            ret = 1;
+        }
+    }
+    if (ret != 0) {
+        printf("Test failed  !!!\n");
+        ret = 1;
+    } else {
+        printf("Test passed !\n");
+    }
+
+    return ret;
+}

fpga/scripts/bd_pcie.tcl

@@ -160,6 +160,7 @@ psi.ch:hls:load_calibration:1.0\
 psi.ch:hls:load_from_hbm:1.0\
 xilinx.com:ip:mailbox:2.1\
 psi.ch:hls:mask_missing:1.0\
+psi.ch:hls:module_upside_down:1.0\
 psi.ch:hls:save_to_hbm:1.0\
 psi.ch:hls:spot_finder:1.0\
 psi.ch:hls:stream_merge:1.0\

fpga/scripts/jfjoch.tcl

@@ -285,12 +285,18 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
 
   # Create instance: axis_data_fifo_11, and set properties
   set axis_data_fifo_11 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_11 ]
+  set_property -dict [ list \
+   CONFIG.FIFO_DEPTH {256} \
+ ] $axis_data_fifo_11
+
+  # Create instance: axis_data_fifo_12, and set properties
+  set axis_data_fifo_12 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_12 ]
   set_property -dict [ list \
    CONFIG.FIFO_DEPTH {32768} \
    CONFIG.FIFO_MEMORY_TYPE {ultra} \
    CONFIG.HAS_AEMPTY {1} \
    CONFIG.HAS_AFULL {1} \
- ] $axis_data_fifo_11
+ ] $axis_data_fifo_12
 
   # Create instance: axis_data_fifo_c2h_cmd, and set properties
   set axis_data_fifo_c2h_cmd [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_c2h_cmd ]
@@ -540,6 +546,9 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   # Create instance: mask_missing_0, and set properties
   set mask_missing_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:mask_missing:1.0 mask_missing_0 ]
 
+  # Create instance: module_upside_down_0, and set properties
+  set module_upside_down_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:module_upside_down:1.0 module_upside_down_0 ]
+
   # Create instance: network_stack
   create_hier_cell_network_stack $hier_obj network_stack
 
@@ -578,7 +587,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   # Create interface connections
   connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins eth_out] [get_bd_intf_pins network_stack/M00_AXIS]
   connect_bd_intf_net -intf_net S_AXIS_1 [get_bd_intf_pins s_axis_h2c_data] [get_bd_intf_pins axis_data_fifo_h2c_data/S_AXIS]
-  connect_bd_intf_net -intf_net add_multipixel_0_data_out [get_bd_intf_pins add_multipixel_0/data_out] [get_bd_intf_pins axis_data_fifo_9/S_AXIS]
+  connect_bd_intf_net -intf_net add_multipixel_0_data_out [get_bd_intf_pins add_multipixel_0/data_out] [get_bd_intf_pins axis_data_fifo_10/S_AXIS]
   connect_bd_intf_net -intf_net adu_histo_0_data_out [get_bd_intf_pins adu_histo_0/data_out] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
   connect_bd_intf_net -intf_net adu_histo_0_m_axis_completion [get_bd_intf_pins adu_histo_0/m_axis_completion] [get_bd_intf_pins axis_compl_fifo_2/S_AXIS]
   connect_bd_intf_net -intf_net adu_histo_0_result_out [get_bd_intf_pins adu_histo_0/result_out] [get_bd_intf_pins axis_adu_histo_result_fifo/S_AXIS]
@@ -600,7 +609,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_intf_net -intf_net axis_compl_fifo_3_M_AXIS [get_bd_intf_pins axis_compl_fifo_5/M_AXIS] [get_bd_intf_pins host_writer_0/s_axis_completion]
   connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins timer_hbm/data_in]
   connect_bd_intf_net -intf_net axis_data_fifo_10_M_AXIS [get_bd_intf_pins axis_spot_finder_fifo_1/M_AXIS] [get_bd_intf_pins host_writer_0/spot_finder_in]
-  connect_bd_intf_net -intf_net axis_data_fifo_10_M_AXIS1 [get_bd_intf_pins axis_data_fifo_10/M_AXIS] [get_bd_intf_pins timer_host/data_in]
+  connect_bd_intf_net -intf_net axis_data_fifo_10_M_AXIS1 [get_bd_intf_pins axis_data_fifo_11/M_AXIS] [get_bd_intf_pins timer_host/data_in]
   connect_bd_intf_net -intf_net axis_data_fifo_12_M_AXIS [get_bd_intf_pins axis_data_fifo_4/M_AXIS] [get_bd_intf_pins mask_missing_0/data_in]
   connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axis_data_fifo_1/M_AXIS] [get_bd_intf_pins axis_register_slice_data_0/S_AXIS]
   connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins axis_data_fifo_2/M_AXIS] [get_bd_intf_pins load_from_hbm_0/data_in]
@@ -608,9 +617,10 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_intf_net -intf_net axis_data_fifo_5_M_AXIS [get_bd_intf_pins axis_data_fifo_5/M_AXIS] [get_bd_intf_pins jf_conversion_0/data_in]
   connect_bd_intf_net -intf_net axis_data_fifo_6_M_AXIS [get_bd_intf_pins axis_data_fifo_6/M_AXIS] [get_bd_intf_pins axis_register_slice_data_1/S_AXIS]
   connect_bd_intf_net -intf_net axis_data_fifo_7_M_AXIS [get_bd_intf_pins axis_data_fifo_7/M_AXIS] [get_bd_intf_pins integration_0/data_in]
-  connect_bd_intf_net -intf_net axis_data_fifo_8_M_AXIS [get_bd_intf_pins add_multipixel_0/data_in] [get_bd_intf_pins axis_data_fifo_8/M_AXIS]
-  connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS [get_bd_intf_pins axis_data_fifo_11/M_AXIS] [get_bd_intf_pins host_writer_0/data_in]
-  connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS1 [get_bd_intf_pins axis_data_fifo_9/M_AXIS] [get_bd_intf_pins bitshuffle_0/data_in]
+  connect_bd_intf_net -intf_net axis_data_fifo_8_M_AXIS [get_bd_intf_pins axis_data_fifo_8/M_AXIS] [get_bd_intf_pins module_upside_down_0/data_in]
+  connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS [get_bd_intf_pins axis_data_fifo_12/M_AXIS] [get_bd_intf_pins host_writer_0/data_in]
+  connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS1 [get_bd_intf_pins axis_data_fifo_10/M_AXIS] [get_bd_intf_pins bitshuffle_0/data_in]
+  connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS2 [get_bd_intf_pins add_multipixel_0/data_in] [get_bd_intf_pins axis_data_fifo_9/M_AXIS]
   connect_bd_intf_net -intf_net axis_data_fifo_c2h_cmd_M_AXIS [get_bd_intf_pins m_axis_c2h_datamover_cmd] [get_bd_intf_pins axis_data_fifo_c2h_cmd/M_AXIS]
   connect_bd_intf_net -intf_net axis_data_fifo_c2h_data_M_AXIS [get_bd_intf_pins m_axis_c2h_data] [get_bd_intf_pins axis_data_fifo_c2h_data/M_AXIS]
   connect_bd_intf_net -intf_net axis_data_fifo_h2c_cmd_M_AXIS [get_bd_intf_pins m_axis_h2c_datamover_cmd] [get_bd_intf_pins axis_data_fifo_h2c_cmd/M_AXIS]
@@ -640,7 +650,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_intf_net -intf_net axis_udp_fifo_0_M_AXIS [get_bd_intf_pins axis_register_slice_udp/S_AXIS] [get_bd_intf_pins axis_udp_fifo_0/M_AXIS]
   connect_bd_intf_net -intf_net axis_work_completion_fifo_0_M_AXIS [get_bd_intf_pins axis_work_completion_fifo_0/M_AXIS] [get_bd_intf_pins mailbox_0/S1_AXIS]
   connect_bd_intf_net -intf_net axis_work_request_fifo_0_M_AXIS [get_bd_intf_pins axis_work_request_fifo_0/M_AXIS] [get_bd_intf_pins host_writer_0/s_axis_work_request]
-  connect_bd_intf_net -intf_net bitshuffle_0_data_out [get_bd_intf_pins axis_data_fifo_10/S_AXIS] [get_bd_intf_pins bitshuffle_0/data_out]
+  connect_bd_intf_net -intf_net bitshuffle_0_data_out [get_bd_intf_pins axis_data_fifo_11/S_AXIS] [get_bd_intf_pins bitshuffle_0/data_out]
   connect_bd_intf_net -intf_net data_collection_fsm_0_addr_out [get_bd_intf_pins axis_addr_fifo_0/S_AXIS] [get_bd_intf_pins data_collection_fsm_0/addr_out]
   connect_bd_intf_net -intf_net data_collection_fsm_0_data_out [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins data_collection_fsm_0/data_out]
   connect_bd_intf_net -intf_net eth_in_1 [get_bd_intf_pins eth_in] [get_bd_intf_pins stream_merge_0/input_1]
@@ -682,6 +692,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_intf_net -intf_net mailbox_0_M1_AXIS [get_bd_intf_pins axis_work_request_fifo_0/S_AXIS] [get_bd_intf_pins mailbox_0/M1_AXIS]
   connect_bd_intf_net -intf_net mask_missing_0_data_out [get_bd_intf_pins axis_data_fifo_5/S_AXIS] [get_bd_intf_pins mask_missing_0/data_out]
   connect_bd_intf_net -intf_net mask_missing_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_3/S_AXIS] [get_bd_intf_pins mask_missing_0/m_axis_completion]
+  connect_bd_intf_net -intf_net module_upside_down_0_data_out [get_bd_intf_pins axis_data_fifo_9/S_AXIS] [get_bd_intf_pins module_upside_down_0/data_out]
   connect_bd_intf_net -intf_net network_stack_udp_addr_out [get_bd_intf_pins axis_udp_addr_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_addr_out]
   connect_bd_intf_net -intf_net network_stack_udp_out [get_bd_intf_pins axis_udp_fifo_0/S_AXIS] [get_bd_intf_pins network_stack/udp_out]
   connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_pins s_axi] [get_bd_intf_pins smartconnect_0/S00_AXI]
@@ -701,7 +712,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_intf_net -intf_net spot_finder_0_strong_pixel_out [get_bd_intf_pins axis_spot_finder_fifo_0/S_AXIS] [get_bd_intf_pins spot_finder_0/strong_pixel_out]
   connect_bd_intf_net -intf_net stream_merge_0_output_r [get_bd_intf_pins axis_eth_in_fifo/S_AXIS] [get_bd_intf_pins stream_merge_0/output_r]
   connect_bd_intf_net -intf_net timer_hbm_data_out [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins timer_hbm/data_out]
-  connect_bd_intf_net -intf_net timer_host_data_out [get_bd_intf_pins axis_data_fifo_11/S_AXIS] [get_bd_intf_pins timer_host/data_out]
+  connect_bd_intf_net -intf_net timer_host_data_out [get_bd_intf_pins axis_data_fifo_12/S_AXIS] [get_bd_intf_pins timer_host/data_out]
 
   # Create port connections
   connect_bd_net -net action_config_0_clear_counters [get_bd_pins action_config_0/clear_counters] [get_bd_pins network_stack/clear_counters]
@@ -717,15 +728,15 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy]
   connect_bd_net -net action_config_0_spot_finder_snr [get_bd_pins action_config_0/spot_finder_snr_threshold] [get_bd_pins spot_finder_0/in_snr_threshold]
   connect_bd_net -net action_config_0_spot_finder_threshold [get_bd_pins action_config_0/spot_finder_count_threshold] [get_bd_pins spot_finder_0/in_count_threshold]
-  connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins add_multipixel_0/ap_clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_128_to_512_0/ap_clk] [get_bd_pins axis_32_to_512_0/ap_clk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_compl_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_10/s_axis_aclk] [get_bd_pins axis_data_fifo_11/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_8/s_axis_aclk] [get_bd_pins axis_data_fifo_9/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_0/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_1/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_2/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aclk] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins bitshuffle_0/ap_clk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins spot_finder_0/ap_clk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
+  connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins add_multipixel_0/ap_clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_128_to_512_0/ap_clk] [get_bd_pins axis_32_to_512_0/ap_clk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aclk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_compl_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_10/s_axis_aclk] [get_bd_pins axis_data_fifo_11/s_axis_aclk] [get_bd_pins axis_data_fifo_12/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_8/s_axis_aclk] [get_bd_pins axis_data_fifo_9/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_0/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_1/s_axis_aclk] [get_bd_pins axis_register_slice_addr_0/aclk] [get_bd_pins axis_register_slice_data_0/aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_2/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aclk] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins bitshuffle_0/ap_clk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins module_upside_down_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins spot_finder_0/ap_clk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
   connect_bd_net -net axis_addr_fifo_0_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_0/almost_empty]
   connect_bd_net -net axis_addr_fifo_0_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_0/almost_full]
   connect_bd_net -net axis_compl_fifo_0_almost_empty [get_bd_pins action_config_0/hbm_compl_fifo_empty] [get_bd_pins axis_compl_fifo_0/almost_empty]
   connect_bd_net -net axis_compl_fifo_0_almost_full [get_bd_pins action_config_0/hbm_compl_fifo_full] [get_bd_pins axis_compl_fifo_0/almost_full]
   connect_bd_net -net axis_compl_fifo_1_almost_empty [get_bd_pins action_config_0/last_addr_fifo_empty] [get_bd_pins axis_compl_fifo_1/almost_empty]
   connect_bd_net -net axis_compl_fifo_1_almost_full [get_bd_pins action_config_0/last_addr_fifo_full] [get_bd_pins axis_compl_fifo_1/almost_full]
-  connect_bd_net -net axis_data_fifo_10_almost_empty [get_bd_pins action_config_0/last_data_fifo_empty] [get_bd_pins axis_data_fifo_11/almost_empty]
-  connect_bd_net -net axis_data_fifo_10_almost_full [get_bd_pins action_config_0/last_data_fifo_full] [get_bd_pins axis_data_fifo_11/almost_full]
+  connect_bd_net -net axis_data_fifo_10_almost_empty [get_bd_pins action_config_0/last_data_fifo_empty] [get_bd_pins axis_data_fifo_12/almost_empty]
+  connect_bd_net -net axis_data_fifo_10_almost_full [get_bd_pins action_config_0/last_data_fifo_full] [get_bd_pins axis_data_fifo_12/almost_full]
   connect_bd_net -net axis_data_fifo_4_almost_empty [get_bd_pins action_config_0/calib_data_fifo_empty] [get_bd_pins axis_data_fifo_1/almost_empty]
   connect_bd_net -net axis_data_fifo_4_almost_full [get_bd_pins action_config_0/calib_data_fifo_full] [get_bd_pins axis_data_fifo_1/almost_full]
   connect_bd_net -net axis_data_fifo_c2h_cmd_almost_empty [get_bd_pins action_config_0/c2h_cmd_fifo_empty] [get_bd_pins axis_data_fifo_c2h_cmd/almost_empty]
@@ -768,9 +779,9 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
   connect_bd_net -net network_stack_packets_sls_ap_vld [get_bd_pins action_config_0/packets_sls_valid] [get_bd_pins network_stack/packets_sls_ap_vld]
   connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp]
   connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld]
-  connect_bd_net -net one_dout [get_bd_pins add_multipixel_0/ap_start] [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins one/dout] [get_bd_pins spot_finder_0/ap_start]
-  connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_compl_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_10/s_axis_aresetn] [get_bd_pins axis_data_fifo_11/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_8/s_axis_aresetn] [get_bd_pins axis_data_fifo_9/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_3/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_0/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_1/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_2/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aresetn] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
-  connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins add_multipixel_0/ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axis_128_to_512_0/ap_rst_n] [get_bd_pins axis_32_to_512_0/ap_rst_n] [get_bd_pins bitshuffle_0/ap_rst_n] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
+  connect_bd_net -net one_dout [get_bd_pins add_multipixel_0/ap_start] [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins module_upside_down_0/ap_start] [get_bd_pins one/dout] [get_bd_pins spot_finder_0/ap_start]
+  connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_compl_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_10/s_axis_aresetn] [get_bd_pins axis_data_fifo_11/s_axis_aresetn] [get_bd_pins axis_data_fifo_12/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_8/s_axis_aresetn] [get_bd_pins axis_data_fifo_9/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_3/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_0/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_1/s_axis_aresetn] [get_bd_pins axis_register_slice_addr_0/aresetn] [get_bd_pins axis_register_slice_data_0/aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_2/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aresetn] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
+  connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins add_multipixel_0/ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axis_128_to_512_0/ap_rst_n] [get_bd_pins axis_32_to_512_0/ap_rst_n] [get_bd_pins bitshuffle_0/ap_rst_n] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins module_upside_down_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
   connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter]
   connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld]
   connect_bd_net -net timer_host_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host/counter]

receiver/HLSSimulatedDevice.cpp

@@ -231,6 +231,7 @@ void HLSSimulatedDevice::HLSMainThread() {
     STREAM_512 converted_8;
     STREAM_512 converted_9;
     STREAM_512 converted_10;
+    STREAM_512 converted_11;
 
     hls::stream<axis_addr> addr0;
     hls::stream<axis_addr> addr1;
@@ -359,18 +360,21 @@ void HLSSimulatedDevice::HLSMainThread() {
 
     hls_cores.emplace_back([&] { axis_128_to_512(integration_result_0, integration_result_1);});
 
-    // 8. Extend multipixels
-    hls_cores.emplace_back([&] { add_multipixel(converted_7, converted_8);});
+    // 8. Invert module upside down
+    hls_cores.emplace_back([&] { module_upside_down(converted_7, converted_8);});
 
-    // 9. Apply bitshuffle
-    hls_cores.emplace_back([&] { bitshuffle(converted_8, converted_9);});
+    // 9. Extend multipixels
+    hls_cores.emplace_back([&] { add_multipixel(converted_8, converted_9);});
+
+    // 10. Apply bitshuffle
+    hls_cores.emplace_back([&] { bitshuffle(converted_9, converted_10);});
 
     // Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
-    hls_cores.emplace_back([&] { timer_host(converted_9, converted_10, counter_host); });
+    hls_cores.emplace_back([&] { timer_host(converted_10, converted_11, counter_host); });
 
-    // 8. Prepare data to write to host memory
+    // 11. Prepare data to write to host memory
     hls_cores.emplace_back([&] {
-        host_writer(converted_10, adu_histo_result, integration_result_1, spot_finder_result_1,
+        host_writer(converted_11, adu_histo_result, integration_result_1, spot_finder_result_1,
                     compl5, datamover_out.GetDataStream(),
                     datamover_out.GetCtrlStream(), work_request_stream, completion_stream,
                     packets_processed, host_writer_idle, err_reg); });
@@ -423,6 +427,18 @@ void HLSSimulatedDevice::HLSMainThread() {
     if (!converted_7.empty())
         throw std::runtime_error("Converted_7 queue not empty");
 
+    if (!converted_8.empty())
+        throw std::runtime_error("Converted_8 queue not empty");
+
+    if (!converted_9.empty())
+        throw std::runtime_error("Converted_9 queue not empty");
+
+    if (!converted_10.empty())
+        throw std::runtime_error("Converted_10 queue not empty");
+
+    if (!converted_11.empty())
+        throw std::runtime_error("Converted_11 queue not empty");
+
     if (!compl0.empty())
         throw std::runtime_error("Compl0 queue not empty");
 
@@ -435,6 +451,12 @@ void HLSSimulatedDevice::HLSMainThread() {
     if (!compl3.empty())
         throw std::runtime_error("Compl3 queue not empty");
 
+    if (!compl4.empty())
+        throw std::runtime_error("Compl4 queue not empty");
+
+    if (!compl5.empty())
+        throw std::runtime_error("Compl5 queue not empty");
+
     if (!hbm_handles.empty())
         throw std::runtime_error("Handles queue not empty");