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FPGA: Clean-up of HDL modules

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This commit is contained in:
leonarski_f
2023-11-18 19:18:26 +01:00
parent ccf5a9ff1a
commit e5397e68cf
7 changed files with 1 additions and 298 deletions
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2
fpga/CMakeLists.txt
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@@ -21,7 +21,7 @@ ADD_SUBDIRECTORY(host_library)
IF(VIVADO_HLS AND VIVADO)
ADD_CUSTOM_COMMAND(OUTPUT action/hw/hdl/action_config.v
COMMAND ${CMAKE_COMMAND} -E env SRC_DIR=${CMAKE_CURRENT_SOURCE_DIR} HLS_IP_DIR=${CMAKE_CURRENT_BINARY_DIR}/action/ip/hls bash ${CMAKE_CURRENT_SOURCE_DIR}/scripts/setup_action.sh
DEPENDS hls hdl/action_config.v hdl/check_datamover_error.v hdl/check_eth_busy.v hdl/gen_xdma_descriptor.v hdl/refclk300to100.v hdl/action_wrapper.v hdl/resetn_sync.v scripts/bd_pcie.tcl scripts/jfjoch.tcl scripts/network_stack.tcl scripts/hbm_u55c.tcl scripts/mac_100g_pcie.tcl scripts/pcie_dma.tcl scripts/setup_action.sh
DEPENDS hls hdl/action_config.v hdl/check_eth_busy.v hdl/gen_xdma_descriptor.v scripts/bd_pcie.tcl scripts/jfjoch.tcl scripts/network_stack.tcl scripts/hbm_u55c.tcl scripts/mac_100g_pcie.tcl scripts/pcie_dma.tcl scripts/setup_action.sh
)
ADD_CUSTOM_TARGET(action_pcie DEPENDS action/hw/hdl/action_config.v hls

202
fpga/hdl/action_wrapper.v
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@@ -1,202 +0,0 @@
// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1 ps / 1 ps
module action_wrapper
( input ap_clk,
input ap_rst_n,
input refclk300_n,
input refclk300_p,
input gt_ref_clk_n,
input gt_ref_clk_p,
input gt_rx_gt_port_0_n,
input gt_rx_gt_port_0_p,
input gt_rx_gt_port_1_n,
input gt_rx_gt_port_1_p,
input gt_rx_gt_port_2_n,
input gt_rx_gt_port_2_p,
input gt_rx_gt_port_3_n,
input gt_rx_gt_port_3_p,
output gt_tx_gt_port_0_n,
output gt_tx_gt_port_0_p,
output gt_tx_gt_port_1_n,
output gt_tx_gt_port_1_p,
output gt_tx_gt_port_2_n,
output gt_tx_gt_port_2_p,
output gt_tx_gt_port_3_n,
output gt_tx_gt_port_3_p,
output interrupt,
input interrupt_ack,
output [8:0] interrupt_ctx,
output [63:0] interrupt_src,
output user_led_a0,
output user_led_a1,
output user_led_g0,
output user_led_g1,
input uc_avr_rx,
output uc_avr_tx,
input uc_avr_ck,
inout qsfpdd_scl,
inout qsfpdd_sda,
input qsfpdd_modprs,
output [63:0] m_axi_host_mem_araddr,
output [1:0] m_axi_host_mem_arburst,
output [3:0] m_axi_host_mem_arcache,
output [3:0] m_axi_host_mem_arid,
output [7:0] m_axi_host_mem_arlen,
output [0:0] m_axi_host_mem_arlock,
output [2:0] m_axi_host_mem_arprot,
output [3:0] m_axi_host_mem_arqos,
input m_axi_host_mem_arready,
output [3:0] m_axi_host_mem_arregion,
output [2:0] m_axi_host_mem_arsize,
output [8:0] m_axi_host_mem_aruser,
output m_axi_host_mem_arvalid,
output [63:0] m_axi_host_mem_awaddr,
output [1:0] m_axi_host_mem_awburst,
output [3:0] m_axi_host_mem_awcache,
output [3:0] m_axi_host_mem_awid,
output [7:0] m_axi_host_mem_awlen,
output [0:0] m_axi_host_mem_awlock,
output [2:0] m_axi_host_mem_awprot,
output [3:0] m_axi_host_mem_awqos,
input m_axi_host_mem_awready,
output [3:0] m_axi_host_mem_awregion,
output [2:0] m_axi_host_mem_awsize,
output [8:0] m_axi_host_mem_awuser,
output m_axi_host_mem_awvalid,
input [3:0] m_axi_host_mem_bid,
output m_axi_host_mem_bready,
input [1:0] m_axi_host_mem_bresp,
input [8:0] m_axi_host_mem_buser,
input m_axi_host_mem_bvalid,
input [1023:0] m_axi_host_mem_rdata,
input [3:0] m_axi_host_mem_rid,
input m_axi_host_mem_rlast,
output m_axi_host_mem_rready,
input [1:0] m_axi_host_mem_rresp,
input [8:0] m_axi_host_mem_ruser,
input m_axi_host_mem_rvalid,
output [1023:0] m_axi_host_mem_wdata,
output m_axi_host_mem_wlast,
input m_axi_host_mem_wready,
output [127:0] m_axi_host_mem_wstrb,
output [8:0] m_axi_host_mem_wuser,
output m_axi_host_mem_wvalid,
input [31:0] s_axi_ctrl_reg_araddr,
input [2:0] s_axi_ctrl_reg_arprot,
output s_axi_ctrl_reg_arready,
input s_axi_ctrl_reg_arvalid,
input [31:0] s_axi_ctrl_reg_awaddr,
input [2:0] s_axi_ctrl_reg_awprot,
output s_axi_ctrl_reg_awready,
input s_axi_ctrl_reg_awvalid,
input s_axi_ctrl_reg_bready,
output [1:0] s_axi_ctrl_reg_bresp,
output s_axi_ctrl_reg_bvalid,
output [31:0] s_axi_ctrl_reg_rdata,
input s_axi_ctrl_reg_rready,
output [1:0] s_axi_ctrl_reg_rresp,
output s_axi_ctrl_reg_rvalid,
input [31:0] s_axi_ctrl_reg_wdata,
output s_axi_ctrl_reg_wready,
input [3:0] s_axi_ctrl_reg_wstrb,
input s_axi_ctrl_reg_wvalid
);
assign m_axi_host_mem_awuser = 0;
assign m_axi_host_mem_aruser = 0;
assign m_axi_host_mem_arlock = 0;
assign m_axi_host_mem_awlock = 0;
assign m_axi_host_mem_arregion = 0;
assign m_axi_host_mem_awregion = 0;
assign m_axi_host_mem_arqos = 0;
assign m_axi_host_mem_awqos = 0;
assign interrupt = 0;
assign interrupt_src = 0;
assign interrupt_ctx = 0;
wire qsfpdd_scl_i;
wire qsfpdd_scl_o;
wire qsfpdd_scl_t;
wire qsfpdd_sda_i;
wire qsfpdd_sda_o;
wire qsfpdd_sda_t;
action action_i
(.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.ref300_clk_n ( refclk300_n ),
.ref300_clk_p ( refclk300_p ),
.gt_ref_clk_n ( gt_ref_clk_n ),
.gt_ref_clk_p ( gt_ref_clk_p ),
.gt_100g_grx_n ({gt_rx_gt_port_3_n,gt_rx_gt_port_2_n,gt_rx_gt_port_1_n,gt_rx_gt_port_0_n}),
.gt_100g_grx_p ({gt_rx_gt_port_3_p,gt_rx_gt_port_2_p,gt_rx_gt_port_1_p,gt_rx_gt_port_0_p}),
.gt_100g_gtx_n ({gt_tx_gt_port_3_n,gt_tx_gt_port_2_n,gt_tx_gt_port_1_n,gt_tx_gt_port_0_n}),
.gt_100g_gtx_p ({gt_tx_gt_port_3_p,gt_tx_gt_port_2_p,gt_tx_gt_port_1_p,gt_tx_gt_port_0_p}),
.qsfpdd_modprs ( qsfpdd_modprs ),
.m_axi_host_mem_araddr ( m_axi_host_mem_araddr),
.m_axi_host_mem_arburst ( m_axi_host_mem_arburst),
.m_axi_host_mem_arcache ( m_axi_host_mem_arcache),
.m_axi_host_mem_arid ( m_axi_host_mem_arid),
.m_axi_host_mem_arlen ( m_axi_host_mem_arlen),
.m_axi_host_mem_arprot ( m_axi_host_mem_arprot),
.m_axi_host_mem_arready ( m_axi_host_mem_arready),
.m_axi_host_mem_arsize ( m_axi_host_mem_arsize),
.m_axi_host_mem_arvalid ( m_axi_host_mem_arvalid),
.m_axi_host_mem_awaddr ( m_axi_host_mem_awaddr),
.m_axi_host_mem_awburst ( m_axi_host_mem_awburst),
.m_axi_host_mem_awcache ( m_axi_host_mem_awcache),
.m_axi_host_mem_awid ( m_axi_host_mem_awid),
.m_axi_host_mem_awlen ( m_axi_host_mem_awlen),
.m_axi_host_mem_awprot ( m_axi_host_mem_awprot),
.m_axi_host_mem_awready ( m_axi_host_mem_awready),
.m_axi_host_mem_awsize ( m_axi_host_mem_awsize),
.m_axi_host_mem_awvalid ( m_axi_host_mem_awvalid),
.m_axi_host_mem_bready ( m_axi_host_mem_bready),
.m_axi_host_mem_bresp ( m_axi_host_mem_bresp),
.m_axi_host_mem_bvalid ( m_axi_host_mem_bvalid),
.m_axi_host_mem_rdata ( m_axi_host_mem_rdata),
.m_axi_host_mem_rlast ( m_axi_host_mem_rlast),
.m_axi_host_mem_rready ( m_axi_host_mem_rready),
.m_axi_host_mem_rresp ( m_axi_host_mem_rresp),
.m_axi_host_mem_rvalid ( m_axi_host_mem_rvalid),
.m_axi_host_mem_wdata ( m_axi_host_mem_wdata),
.m_axi_host_mem_wlast ( m_axi_host_mem_wlast),
.m_axi_host_mem_wready ( m_axi_host_mem_wready),
.m_axi_host_mem_wstrb ( m_axi_host_mem_wstrb),
.m_axi_host_mem_wvalid ( m_axi_host_mem_wvalid),
.s_axi_ctrl_reg_araddr ( s_axi_ctrl_reg_araddr),
.s_axi_ctrl_reg_arprot ( s_axi_ctrl_reg_arprot),
.s_axi_ctrl_reg_arready ( s_axi_ctrl_reg_arready),
.s_axi_ctrl_reg_arvalid ( s_axi_ctrl_reg_arvalid),
.s_axi_ctrl_reg_awaddr ( s_axi_ctrl_reg_awaddr),
.s_axi_ctrl_reg_awprot ( s_axi_ctrl_reg_awprot),
.s_axi_ctrl_reg_awready ( s_axi_ctrl_reg_awready),
.s_axi_ctrl_reg_awvalid ( s_axi_ctrl_reg_awvalid),
.s_axi_ctrl_reg_bready ( s_axi_ctrl_reg_bready),
.s_axi_ctrl_reg_bresp ( s_axi_ctrl_reg_bresp),
.s_axi_ctrl_reg_bvalid ( s_axi_ctrl_reg_bvalid),
.s_axi_ctrl_reg_rdata ( s_axi_ctrl_reg_rdata),
.s_axi_ctrl_reg_rready ( s_axi_ctrl_reg_rready),
.s_axi_ctrl_reg_rresp ( s_axi_ctrl_reg_rresp),
.s_axi_ctrl_reg_rvalid ( s_axi_ctrl_reg_rvalid),
.s_axi_ctrl_reg_wdata ( s_axi_ctrl_reg_wdata),
.s_axi_ctrl_reg_wready ( s_axi_ctrl_reg_wready),
.s_axi_ctrl_reg_wstrb ( s_axi_ctrl_reg_wstrb),
.s_axi_ctrl_reg_wvalid ( s_axi_ctrl_reg_wvalid),
.uc_avr_rx ( uc_avr_rx),
.uc_avr_tx ( uc_avr_tx),
.uc_avr_ck ( uc_avr_ck),
.user_led_a0 ( user_led_a0),
.user_led_a1 ( user_led_a1),
.user_led_g0 ( user_led_g0),
.user_led_g1 ( user_led_g1));
endmodule

37
fpga/hdl/check_datamover_error.v
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@@ -1,37 +0,0 @@
// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
module check_datamover_error(
output reg err_encountered,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET resetn, ASSOCIATED_BUSIF S_AXIS" *)
input clk,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 resetn RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input resetn,
(* X_INTERFACE_PARAMETER = "HAS_TLAST 1,HAS_TKEEP 1,HAS_TREADY 1,TUSER_WIDTH 0,TDATA_NUM_BYTES 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input [7:0] S_AXIS_tdata,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
input S_AXIS_tkeep,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input S_AXIS_tlast,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input S_AXIS_tvalid,
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output S_AXIS_tready
);
assign S_AXIS_tready = resetn;
always @(posedge clk) begin
if (!resetn)
err_encountered <= 0;
else if (S_AXIS_tvalid)
err_encountered <= !S_AXIS_tdata[7];
end
endmodule

22
fpga/hdl/refclk300to100.v
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@@ -1,22 +0,0 @@
// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
module refclk300to100 (
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 refclk300 CLK" *)
(* X_INTERFACE_PARAMETER = "FREQ_HZ 300000000" *)
input refclk300,
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 refclk100 CLK" *)
(* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *)
output refclk100
);
BUFGCE_DIV #(
.BUFGCE_DIVIDE(3)
)
BUFGCE_DIV_inst (
.O(refclk100),
.CE(1'b1),
.CLR(1'b0),
.I(refclk300)
);
endmodule

34
fpga/hdl/resetn_sync.v
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@@ -1,34 +0,0 @@
// Copyright (2019-2023) Paul Scherrer Institute
`timescale 1ns / 1ps
module resetn_sync (
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
(* X_INTERFACE_PARAMETER = "ASSOCIATED_RESET out_resetn" *)
input clk,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 in_resetn RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input in_resetn,
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 out_resetn RST" *)
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
output out_resetn
);
(* ASYNC_REG = "TRUE" *) reg q0, q1, q2;
always @(posedge clk or negedge in_resetn)
if (~in_resetn)
q0 <= 1'b0;
else
q0 <= in_resetn;
always @(posedge clk)
begin
q1 <= q0;
q2 <= q1;
end
assign out_resetn = q2;
endmodule

1
fpga/scripts/bd_pcie.tcl
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@@ -205,7 +205,6 @@ if { $bCheckModules == 1 } {
gen_xdma_descriptor\
action_config\
check_eth_busy\
resetn_sync\
"
set list_mods_missing ""

1
fpga/scripts/build_pcie_design.tcl
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@@ -20,7 +20,6 @@ set source_set [get_filesets sources_1]
set hdl_files [list \
[file normalize "action/hw/hdl/action_config.v"] \
[file normalize "action/hw/hdl/resetn_sync.v"] \
[file normalize "action/hw/hdl/check_eth_busy.v"] \
[file normalize "action/hw/hdl/gen_xdma_descriptor.v"] \
]