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FPGA: Remove bitshuffle from the pipeline

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This commit is contained in:
leonarski_f
2023-10-27 19:41:02 +02:00
parent f46a8e47a0
commit c896ec5659
3 changed files with 13 additions and 58 deletions
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fpga/scripts/image_processing.tcl
+5 -16
View File
@@ -161,12 +161,6 @@ proc create_hier_cell_image_processing { parentCell nameHier } {
CONFIG.FIFO_DEPTH {256} \
] $axis_data_fifo_9
# Create instance: axis_data_fifo_10, and set properties
set axis_data_fifo_10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_10 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
] $axis_data_fifo_10
# Create instance: axis_integration_result_fifo_0, and set properties
set axis_integration_result_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_integration_result_fifo_0 ]
set_property -dict [ list \
@@ -216,9 +210,6 @@ proc create_hier_cell_image_processing { parentCell nameHier } {
CONFIG.FIFO_DEPTH {16} \
] $axis_spot_finder_fifo_1
# Create instance: bitshuffle_0, and set properties
set bitshuffle_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:bitshuffle:1.0 bitshuffle_0 ]
# Create instance: frame_summation_0, and set properties
set frame_summation_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:frame_summation:1.0 frame_summation_0 ]
@@ -251,7 +242,6 @@ proc create_hier_cell_image_processing { parentCell nameHier } {
connect_bd_intf_net -intf_net Conn17 [get_bd_intf_pins s_axis_completion] [get_bd_intf_pins adu_histo_0/s_axis_completion]
connect_bd_intf_net -intf_net Conn19 [get_bd_intf_pins result_out] [get_bd_intf_pins adu_histo_0/result_out]
connect_bd_intf_net -intf_net Conn21 [get_bd_intf_pins m_axi_d_hbm_p6] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p6]
connect_bd_intf_net -intf_net Conn22 [get_bd_intf_pins data_out] [get_bd_intf_pins bitshuffle_0/data_out]
connect_bd_intf_net -intf_net Conn23 [get_bd_intf_pins m_axi_d_hbm_p7] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p7]
connect_bd_intf_net -intf_net Conn24 [get_bd_intf_pins m_axis_completion] [get_bd_intf_pins frame_summation_0/m_axis_completion]
connect_bd_intf_net -intf_net Conn25 [get_bd_intf_pins data_in] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
@@ -261,7 +251,7 @@ proc create_hier_cell_image_processing { parentCell nameHier } {
connect_bd_intf_net -intf_net Conn29 [get_bd_intf_pins m_axi_d_hbm_p11] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p11]
connect_bd_intf_net -intf_net Conn30 [get_bd_intf_pins m_axi_d_hbm_p2] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p2]
connect_bd_intf_net -intf_net Conn31 [get_bd_intf_pins m_axi_d_hbm_p1] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p1]
connect_bd_intf_net -intf_net add_multipixel_0_data_out [get_bd_intf_pins add_multipixel_0/data_out] [get_bd_intf_pins axis_data_fifo_10/S_AXIS]
connect_bd_intf_net -intf_net add_multipixel_0_data_out [get_bd_intf_pins data_out] [get_bd_intf_pins add_multipixel_0/data_out]
connect_bd_intf_net -intf_net adu_histo_0_data_out [get_bd_intf_pins adu_histo_0/data_out] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
connect_bd_intf_net -intf_net adu_histo_0_m_axis_completion [get_bd_intf_pins adu_histo_0/m_axis_completion] [get_bd_intf_pins axis_compl_fifo_2/S_AXIS]
connect_bd_intf_net -intf_net axis_128_to_512_0_data_out [get_bd_intf_pins axis_128_to_512_0/data_out] [get_bd_intf_pins axis_integration_result_fifo_1/S_AXIS]
@@ -277,7 +267,6 @@ proc create_hier_cell_image_processing { parentCell nameHier } {
connect_bd_intf_net -intf_net axis_data_fifo_7_M_AXIS [get_bd_intf_pins axis_data_fifo_7/M_AXIS] [get_bd_intf_pins frame_summation_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_8_M_AXIS [get_bd_intf_pins axis_data_fifo_8/M_AXIS] [get_bd_intf_pins spot_finder_0/data_in]
connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS [get_bd_intf_pins add_multipixel_0/data_in] [get_bd_intf_pins axis_data_fifo_9/M_AXIS]
connect_bd_intf_net -intf_net axis_data_fifo_9_M_AXIS1 [get_bd_intf_pins axis_data_fifo_10/M_AXIS] [get_bd_intf_pins bitshuffle_0/data_in]
connect_bd_intf_net -intf_net axis_integration_result_fifo_0_M_AXIS [get_bd_intf_pins axis_128_to_512_0/data_in] [get_bd_intf_pins axis_integration_result_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_data_1_M_AXIS [get_bd_intf_pins axis_register_slice_data_1/M_AXIS] [get_bd_intf_pins integration_0/data_in]
connect_bd_intf_net -intf_net axis_register_slice_data_2_M_AXIS [get_bd_intf_pins axis_data_fifo_7/S_AXIS] [get_bd_intf_pins axis_register_slice_data_2/M_AXIS]
@@ -295,14 +284,14 @@ proc create_hier_cell_image_processing { parentCell nameHier } {
connect_bd_intf_net -intf_net spot_finder_0_strong_pixel_out [get_bd_intf_pins axis_spot_finder_fifo_0/S_AXIS] [get_bd_intf_pins spot_finder_0/strong_pixel_out]
# Create port connections
connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins add_multipixel_0/ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axis_128_to_512_0/ap_rst_n] [get_bd_pins axis_32_to_512_0/ap_rst_n] [get_bd_pins bitshuffle_0/ap_rst_n] [get_bd_pins frame_summation_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n]
connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins add_multipixel_0/ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axis_128_to_512_0/ap_rst_n] [get_bd_pins axis_32_to_512_0/ap_rst_n] [get_bd_pins frame_summation_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n]
connect_bd_net -net ap_start_1 [get_bd_pins add_multipixel_0/ap_start] [get_bd_pins frame_summation_0/ap_start] [get_bd_pins one/dout] [get_bd_pins spot_finder_0/ap_start]
connect_bd_net -net axi_clk_1 [get_bd_pins axi_clk] [get_bd_pins add_multipixel_0/ap_clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axis_128_to_512_0/ap_clk] [get_bd_pins axis_32_to_512_0/ap_clk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_compl_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_10/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_8/s_axis_aclk] [get_bd_pins axis_data_fifo_9/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_0/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_1/s_axis_aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_2/aclk] [get_bd_pins axis_register_slice_data_3/aclk] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aclk] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aclk] [get_bd_pins bitshuffle_0/ap_clk] [get_bd_pins frame_summation_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins spot_finder_0/ap_clk]
connect_bd_net -net axi_rst_n_1 [get_bd_pins axi_rst_n] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_compl_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_10/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_8/s_axis_aresetn] [get_bd_pins axis_data_fifo_9/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_0/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_1/s_axis_aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_2/aresetn] [get_bd_pins axis_register_slice_data_3/aresetn] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aresetn] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aresetn]
connect_bd_net -net axi_clk_1 [get_bd_pins axi_clk] [get_bd_pins add_multipixel_0/ap_clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axis_128_to_512_0/ap_clk] [get_bd_pins axis_32_to_512_0/ap_clk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_compl_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_8/s_axis_aclk] [get_bd_pins axis_data_fifo_9/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_0/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_1/s_axis_aclk] [get_bd_pins axis_register_slice_data_1/aclk] [get_bd_pins axis_register_slice_data_2/aclk] [get_bd_pins axis_register_slice_data_3/aclk] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aclk] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aclk] [get_bd_pins frame_summation_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins spot_finder_0/ap_clk]
connect_bd_net -net axi_rst_n_1 [get_bd_pins axi_rst_n] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_compl_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_8/s_axis_aresetn] [get_bd_pins axis_data_fifo_9/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_0/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_1/s_axis_aresetn] [get_bd_pins axis_register_slice_data_1/aresetn] [get_bd_pins axis_register_slice_data_2/aresetn] [get_bd_pins axis_register_slice_data_3/aresetn] [get_bd_pins axis_spot_finder_fifo_0/s_axis_aresetn] [get_bd_pins axis_spot_finder_fifo_1/s_axis_aresetn]
connect_bd_net -net hbm_size_bytes_1 [get_bd_pins hbm_size_bytes] [get_bd_pins integration_0/hbm_size_bytes] [get_bd_pins jf_conversion_0/hbm_size_bytes]
connect_bd_net -net in_count_threshold_1 [get_bd_pins in_count_threshold] [get_bd_pins spot_finder_0/in_count_threshold]
connect_bd_net -net in_snr_threshold_1 [get_bd_pins in_snr_threshold] [get_bd_pins spot_finder_0/in_snr_threshold]
# Restore current instance
current_bd_instance $oldCurInst
}
}
receiver/HLSSimulatedDevice.cpp
+8 -5
View File
@@ -369,15 +369,12 @@ void HLSSimulatedDevice::HLSMainThread() {
// 9. Extend multipixels
hls_cores.emplace_back([&] { add_multipixel(converted_9, converted_10);});
// 10. Apply bitshuffle
hls_cores.emplace_back([&] { bitshuffle(converted_10, converted_11);});
// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { timer_host(converted_11, converted_12, counter_host); });
hls_cores.emplace_back([&] { timer_host(converted_10, converted_11, counter_host); });
// 11. Prepare data to write to host memory
hls_cores.emplace_back([&] {
host_writer(converted_12, adu_histo_result, integration_result_1, spot_finder_result_1,
host_writer(converted_11, adu_histo_result, integration_result_1, spot_finder_result_1,
compl7, datamover_out.GetDataStream(),
datamover_out.GetCtrlStream(), work_request_stream, completion_stream,
packets_processed, host_writer_idle, err_reg); });
@@ -460,6 +457,12 @@ void HLSSimulatedDevice::HLSMainThread() {
if (!compl5.empty())
throw std::runtime_error("Compl5 queue not empty");
if (!compl6.empty())
throw std::runtime_error("Compl6 queue not empty");
if (!compl7.empty())
throw std::runtime_error("Compl7 queue not empty");
if (!hbm_handles.empty())
throw std::runtime_error("Handles queue not empty");
tests/FPGAIntegrationTest.cpp
-37
View File
@@ -1235,40 +1235,3 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_snr_threshold"
REQUIRE (spot_finder_result.strong_pixel[0] == (1<<0));
REQUIRE (spot_finder_result.strong_pixel[(89*1024 + 300) / 8] == (1<<4)); // 300 % 8 == 4
}
TEST_CASE("HLS_C_Simulation_bitsuffle", "[FPGA][Full]") {
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
std::vector<uint16_t> input_frame(FRAME_GENERATOR_MODULES*RAW_MODULE_SIZE);
std::mt19937 g1(1387);
std::uniform_int_distribution<uint16_t> dist(0, 65535);
for (auto &i: input_frame)
i = dist(g1);
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
HLSSimulatedDevice test(0, 64);
test.SetInternalGeneratorFrame(input_frame);
REQUIRE_NOTHROW(test.StartAction(x, MODE_BITSHUFFLE_FPGA));
REQUIRE_NOTHROW(test.WaitForActionComplete());
REQUIRE(test.OutputStream().size() == 1);
REQUIRE(test.GetBytesReceived() == 128 * nmodules * 4 * JUNGFRAU_PACKET_SIZE_BYTES);
for (int image = 0; image < 4; image++) {
for (int m = 0; m < nmodules; m++) {
auto imageBuf = (uint16_t *) test.GetDeviceOutput(image, m)->pixels;
std::vector<uint16_t> image_out_unshuf(RAW_MODULE_SIZE);
bshuf_bitunshuffle(imageBuf, image_out_unshuf.data(), RAW_MODULE_SIZE, sizeof(uint16_t), 2048);
for (int i = 0; i < RAW_MODULE_SIZE; i++) {
REQUIRE(image_out_unshuf[i] == input_frame[m * RAW_MODULE_SIZE + i]);
}
}
}
}