mx/Jungfraujoch
2
1
Fork 0
Code Issues Pull Requests Actions 2 Packages Projects Releases 67 Wiki Activity

FPGA: integration results are reduced to cover two bins per 512-bit

Browse Source
This commit is contained in:
leonarski_f
2023-09-29 22:07:52 +02:00
parent 8831ad380f
commit ca118f26d5
9 changed files with 87 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files
fpga/hls/CMakeLists.txt
+4 -1
View File
@@ -20,7 +20,8 @@ ADD_LIBRARY( HLSSimulation STATIC
mask_missing.cpp
spot_finder.cpp
axis_broadcast.cpp
adu_histo.cpp)
adu_histo.cpp
axis_256_to_512.cpp)
TARGET_INCLUDE_DIRECTORIES(HLSSimulation PUBLIC ../include)
TARGET_LINK_LIBRARIES(HLSSimulation CommonFunctions)
@@ -59,6 +60,7 @@ MAKE_HLS_MODULE(mask_missing.cpp mask_missing)
MAKE_HLS_MODULE(integration.cpp integration)
MAKE_HLS_MODULE(spot_finder.cpp spot_finder)
MAKE_HLS_MODULE(axis_broadcast.cpp axis_broadcast)
MAKE_HLS_MODULE(axis_256_to_512.cpp axis_256_to_512)
MAKE_HLS_MODULE(adu_histo.cpp adu_histo)
SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip
@@ -79,6 +81,7 @@ SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip
psi_ch_hls_spot_finder_1_0.zip
psi_ch_hls_integration_1_0.zip
psi_ch_hls_axis_broadcast_1_0.zip
psi_ch_hls_axis_256_to_512_1_0.zip
psi_ch_hls_adu_histo_1_0.zip
psi_ch_hls_stream_merge_1_0.zip)
fpga/hls/axis_256_to_512.cpp
+23
View File
@@ -0,0 +1,23 @@
// Copyright (2019-2023) Paul Scherrer Institute
#include "hls_jfjoch.h"
void axis_256_to_512(hls::stream<ap_axiu<256,1,1,1>> &data_in,
hls::stream<ap_uint<512>> &data_out) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE axis register both port=data_in
#pragma HLS INTERFACE axis register both port=data_out
ap_axiu<256,1,1,1> packet_256[2];
data_in >> packet_256[0];
while (!packet_256[0].user) {
#pragma HLS PIPELINE II=2
data_in >> packet_256[1];
data_out << (packet_256[1].data,packet_256[0].data);
data_in >> packet_256[0];
}
}
fpga/hls/hls_jfjoch.h
+5 -2
View File
@@ -135,7 +135,7 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
void host_writer(STREAM_512 &data_in,
hls::stream<ap_uint<512>> &adu_histo_in,
hls::stream<ap_uint<192>> &integration_in,
hls::stream<ap_uint<512>> &integration_in,
hls::stream<ap_uint<512>> &spot_finder_in,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<ap_axiu<512,1,1,1> > &host_memory_out,
@@ -183,13 +183,16 @@ void stream_merge(AXI_STREAM &input_0,
void integration(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<ap_uint<192>> &result_out,
hls::stream<ap_axiu<256,1,1,1>> &result_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<32> hbm_size_bytes);
void axis_256_to_512(hls::stream<ap_axiu<256,1,1,1>> &data_in,
hls::stream<ap_uint<512>> &data_out);
void spot_finder(STREAM_512 &data_in,
hls::stream<ap_uint<512>> &result_out);
fpga/hls/host_writer.cpp
+4 -6
View File
@@ -75,7 +75,7 @@ inline ap_uint<1> read_request(hls::stream<ap_uint<32> > &s_axis_work_request,
void host_writer(STREAM_512 &data_in,
hls::stream<ap_uint<512>> &adu_histo_in,
hls::stream<ap_uint<192>> &integration_in,
hls::stream<ap_uint<512>> &integration_in,
hls::stream<ap_uint<512>> &spot_finder_in,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<ap_axiu<512,1,1,1> > &host_memory_out,
@@ -130,7 +130,7 @@ void host_writer(STREAM_512 &data_in,
read_request(s_axis_work_request, req_handle, req_host_offset);
setup_datamover(datamover_out_cmd, req_host_offset,
RAW_MODULE_SIZE * sizeof(uint16_t) * (16 + 1) / 16
+ (FPGA_INTEGRATION_BIN_COUNT)*64
+ (FPGA_INTEGRATION_BIN_COUNT/2)*64
+ ADU_HISTO_BIN_COUNT / 16 * 64);
packet_512_t packet_out;
@@ -154,11 +154,9 @@ void host_writer(STREAM_512 &data_in,
host_memory_out << packet_out;
}
for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT; i++) {
for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT / 2; i++) {
#pragma HLS PIPELINE II=1
ap_uint<192> tmp;
integration_in >> tmp;
packet_out.data = tmp;
integration_in >> packet_out.data;
host_memory_out << packet_out;
}
fpga/hls/integration.cpp
+15 -7
View File
@@ -4,7 +4,7 @@
void integration(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<ap_uint<192>> &result_out,
hls::stream<ap_axiu<256,1,1,1>> &result_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion,
ap_uint<256> *d_hbm_p0,
@@ -82,7 +82,7 @@ void integration(STREAM_512 &data_in,
for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT; i++) {
#pragma HLS PIPELINE II=1
ap_uint<192> val = 0;
ap_axiu<256,1,1,1> res;
ap_int<38> main_sum = 0;
ap_int<52> main_sum2 = 0;
ap_int<22> main_count = 0;
@@ -93,17 +93,25 @@ void integration(STREAM_512 &data_in,
sum[j][i] = 0;
sum2[j][i] = 0;
count[j][i] = 0;
}
val(63, 0 ) = main_count;
val(127, 64) = main_sum;
val(191, 128) = main_sum2;
result_out << val;
res.data(63, 0) = main_count;
res.data(127, 64) = main_sum;
res.data(191, 128) = main_sum2;
res.data(255, 192) = 0;
res.dest = 0;
res.id = 0;
res.keep = UINT32_MAX;
res.strb = UINT32_MAX;
res.user = 0;
res.last = ((i == FPGA_INTEGRATION_BIN_COUNT - 1) ? 1 : 0);
result_out << res;
}
s_axis_completion >> cmpl;
}
m_axis_completion << cmpl;
result_out << ap_axiu<256,1,1,1>{.user = 1};
data_in >> packet_in;
data_out << packet_in;
}
fpga/scripts/bd_pcie.tcl
+1
View File
@@ -145,6 +145,7 @@ xilinx.com:ip:hbm:1.0\
xilinx.com:ip:util_vector_logic:2.0\
psi.ch:hls:adu_histo:1.0\
xilinx.com:ip:axi_datamover:5.1\
psi.ch:hls:axis_256_to_512:1.0\
xilinx.com:ip:axis_data_fifo:2.0\
psi.ch:hls:axis_broadcast:1.0\
xilinx.com:ip:axis_register_slice:1.1\
fpga/scripts/jfjoch.tcl
+22 -8
View File
@@ -151,6 +151,9 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.c_single_interface {0} \
] $axi_datamover_1
# Create instance: axis_256_to_512_0, and set properties
set axis_256_to_512_0 [ create_bd_cell -type ip -vlnv psi.ch:hls:axis_256_to_512:1.0 axis_256_to_512_0 ]
# Create instance: axis_addr_fifo_0, and set properties
set axis_addr_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_addr_fifo_0 ]
set_property -dict [ list \
@@ -386,14 +389,23 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
CONFIG.HAS_AFULL {1} \
] $axis_hbm_handles_fifo
# Create instance: axis_integration_result_fifo, and set properties
set axis_integration_result_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_integration_result_fifo ]
# Create instance: axis_integration_result_fifo_0, and set properties
set axis_integration_result_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_integration_result_fifo_0 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {auto} \
CONFIG.HAS_AEMPTY {0} \
CONFIG.HAS_AFULL {0} \
] $axis_integration_result_fifo
] $axis_integration_result_fifo_0
# Create instance: axis_integration_result_fifo_1, and set properties
set axis_integration_result_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_integration_result_fifo_1 ]
set_property -dict [ list \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MEMORY_TYPE {auto} \
CONFIG.HAS_AEMPTY {0} \
CONFIG.HAS_AFULL {0} \
] $axis_integration_result_fifo_1
# Create instance: axis_register_slice_0, and set properties
set axis_register_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_register_slice:1.1 axis_register_slice_0 ]
@@ -538,6 +550,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net axi_datamover_1_M_AXIS_MM2S [get_bd_intf_pins axi_datamover_1/M_AXIS_MM2S] [get_bd_intf_pins axis_datamover_fifo_3/S_AXIS]
connect_bd_intf_net -intf_net axi_datamover_1_M_AXI_MM2S [get_bd_intf_pins m_axi_d_hbm_p14] [get_bd_intf_pins axi_datamover_1/M_AXI_MM2S]
connect_bd_intf_net -intf_net axi_datamover_1_M_AXI_S2MM [get_bd_intf_pins m_axi_d_hbm_p15] [get_bd_intf_pins axi_datamover_1/M_AXI_S2MM]
connect_bd_intf_net -intf_net axis_256_to_512_0_data_out [get_bd_intf_pins axis_256_to_512_0/data_out] [get_bd_intf_pins axis_integration_result_fifo_1/S_AXIS]
connect_bd_intf_net -intf_net axis_addr_fifo_0_M_AXIS [get_bd_intf_pins axis_addr_fifo_0/M_AXIS] [get_bd_intf_pins axis_register_slice_1/S_AXIS]
connect_bd_intf_net -intf_net axis_adu_histo_result_fifo_M_AXIS [get_bd_intf_pins axis_adu_histo_result_fifo/M_AXIS] [get_bd_intf_pins host_writer_0/adu_histo_in]
connect_bd_intf_net -intf_net axis_broadcast_0_data_out_0 [get_bd_intf_pins axis_broadcast_0/data_out_0] [get_bd_intf_pins axis_data_fifo_7/S_AXIS]
@@ -575,7 +588,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net axis_eth_in_fifo_M_AXIS [get_bd_intf_pins axis_eth_in_fifo/M_AXIS] [get_bd_intf_pins network_stack/eth_in]
connect_bd_intf_net -intf_net axis_frame_generator_fifo_0_M_AXIS [get_bd_intf_pins axis_frame_generator_fifo_0/M_AXIS] [get_bd_intf_pins stream_merge_0/input_0]
connect_bd_intf_net -intf_net axis_hbm_handles_fifo_M_AXIS [get_bd_intf_pins axis_hbm_handles_fifo/M_AXIS] [get_bd_intf_pins save_to_hbm_0/s_axis_free_handles]
connect_bd_intf_net -intf_net axis_integration_result_fifo_M_AXIS [get_bd_intf_pins axis_integration_result_fifo/M_AXIS] [get_bd_intf_pins host_writer_0/integration_in]
connect_bd_intf_net -intf_net axis_integration_result_fifo1_M_AXIS [get_bd_intf_pins axis_integration_result_fifo_1/M_AXIS] [get_bd_intf_pins host_writer_0/integration_in]
connect_bd_intf_net -intf_net axis_integration_result_fifo_M_AXIS [get_bd_intf_pins axis_256_to_512_0/data_in] [get_bd_intf_pins axis_integration_result_fifo_0/M_AXIS]
connect_bd_intf_net -intf_net axis_register_slice_0_M_AXIS [get_bd_intf_pins axis_register_slice_0/M_AXIS] [get_bd_intf_pins save_to_hbm_0/data_in]
connect_bd_intf_net -intf_net axis_register_slice_1_M_AXIS [get_bd_intf_pins axis_register_slice_1/M_AXIS] [get_bd_intf_pins save_to_hbm_0/addr_in]
connect_bd_intf_net -intf_net axis_register_slice_data_in_0_M_AXIS1 [get_bd_intf_pins axis_register_slice_data_in_0/M_AXIS] [get_bd_intf_pins load_calibration_0/host_memory_in]
@@ -598,7 +612,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_intf_net -intf_net integration_0_m_axi_d_hbm_p0 [get_bd_intf_pins m_axi_d_hbm_p16] [get_bd_intf_pins integration_0/m_axi_d_hbm_p0]
connect_bd_intf_net -intf_net integration_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p17] [get_bd_intf_pins integration_0/m_axi_d_hbm_p1]
connect_bd_intf_net -intf_net integration_0_m_axis_completion [get_bd_intf_pins axis_compl_fifo_5/S_AXIS] [get_bd_intf_pins integration_0/m_axis_completion]
connect_bd_intf_net -intf_net integration_0_result_out [get_bd_intf_pins axis_integration_result_fifo/S_AXIS] [get_bd_intf_pins integration_0/result_out]
connect_bd_intf_net -intf_net integration_0_result_out [get_bd_intf_pins axis_integration_result_fifo_0/S_AXIS] [get_bd_intf_pins integration_0/result_out]
connect_bd_intf_net -intf_net jf_conversion_0_data_out [get_bd_intf_pins axis_data_fifo_6/S_AXIS] [get_bd_intf_pins jf_conversion_0/data_out]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p0 [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p0] [get_bd_intf_pins smartconnect_1/S00_AXI]
connect_bd_intf_net -intf_net jf_conversion_0_m_axi_d_hbm_p1 [get_bd_intf_pins m_axi_d_hbm_p1] [get_bd_intf_pins jf_conversion_0/m_axi_d_hbm_p1]
@@ -656,7 +670,7 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net action_config_0_nmodules [get_bd_pins action_config_0/nmodules] [get_bd_pins data_collection_fsm_0/nmodules]
connect_bd_net -net action_config_0_nstorage_cells [get_bd_pins action_config_0/nstorage_cells] [get_bd_pins data_collection_fsm_0/nstorage_cells]
connect_bd_net -net action_config_0_one_over_energy [get_bd_pins action_config_0/one_over_energy] [get_bd_pins data_collection_fsm_0/one_over_energy]
connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aclk] [get_bd_pins axis_broadcast_0/ap_clk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_compl_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_10/s_axis_aclk] [get_bd_pins axis_data_fifo_11/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_8/s_axis_aclk] [get_bd_pins axis_data_fifo_9/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_integration_result_fifo/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins spot_finder_0/ap_clk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
connect_bd_net -net ap_clk_1 [get_bd_pins axi_clk] [get_bd_pins action_config_0/clk] [get_bd_pins adu_histo_0/ap_clk] [get_bd_pins axi_datamover_0/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_datamover_1/m_axi_mm2s_aclk] [get_bd_pins axi_datamover_1/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aclk] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axis_256_to_512_0/ap_clk] [get_bd_pins axis_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aclk] [get_bd_pins axis_broadcast_0/ap_clk] [get_bd_pins axis_compl_fifo_0/s_axis_aclk] [get_bd_pins axis_compl_fifo_1/s_axis_aclk] [get_bd_pins axis_compl_fifo_2/s_axis_aclk] [get_bd_pins axis_compl_fifo_3/s_axis_aclk] [get_bd_pins axis_compl_fifo_4/s_axis_aclk] [get_bd_pins axis_compl_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_10/s_axis_aclk] [get_bd_pins axis_data_fifo_11/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_data_fifo_5/s_axis_aclk] [get_bd_pins axis_data_fifo_6/s_axis_aclk] [get_bd_pins axis_data_fifo_7/s_axis_aclk] [get_bd_pins axis_data_fifo_8/s_axis_aclk] [get_bd_pins axis_data_fifo_9/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aclk] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aclk] [get_bd_pins axis_datamover_fifo_0/s_axis_aclk] [get_bd_pins axis_datamover_fifo_1/s_axis_aclk] [get_bd_pins axis_datamover_fifo_2/s_axis_aclk] [get_bd_pins axis_datamover_fifo_3/s_axis_aclk] [get_bd_pins axis_eth_in_fifo/s_axis_aclk] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aclk] [get_bd_pins axis_hbm_handles_fifo/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_0/s_axis_aclk] [get_bd_pins axis_integration_result_fifo_1/s_axis_aclk] [get_bd_pins axis_register_slice_0/aclk] [get_bd_pins axis_register_slice_1/aclk] [get_bd_pins axis_register_slice_data_in_0/aclk] [get_bd_pins axis_register_slice_host_mem/aclk] [get_bd_pins axis_register_slice_udp/aclk] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aclk] [get_bd_pins axis_udp_fifo_0/s_axis_aclk] [get_bd_pins axis_work_completion_fifo_0/s_axis_aclk] [get_bd_pins axis_work_request_fifo_0/s_axis_aclk] [get_bd_pins data_collection_fsm_0/ap_clk] [get_bd_pins frame_generator_0/ap_clk] [get_bd_pins host_writer_0/ap_clk] [get_bd_pins integration_0/ap_clk] [get_bd_pins jf_conversion_0/ap_clk] [get_bd_pins load_calibration_0/ap_clk] [get_bd_pins load_from_hbm_0/ap_clk] [get_bd_pins mailbox_0/M1_AXIS_ACLK] [get_bd_pins mailbox_0/S0_AXI_ACLK] [get_bd_pins mailbox_0/S1_AXIS_ACLK] [get_bd_pins mask_missing_0/ap_clk] [get_bd_pins network_stack/axiclk] [get_bd_pins save_to_hbm_0/ap_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins smartconnect_1/aclk] [get_bd_pins smartconnect_2/aclk] [get_bd_pins spot_finder_0/ap_clk] [get_bd_pins stream_merge_0/ap_clk] [get_bd_pins timer_hbm/ap_clk] [get_bd_pins timer_host/ap_clk]
connect_bd_net -net axis_addr_fifo_0_almost_empty [get_bd_pins action_config_0/calib_addr_fifo_empty] [get_bd_pins axis_addr_fifo_0/almost_empty]
connect_bd_net -net axis_addr_fifo_0_almost_full [get_bd_pins action_config_0/calib_addr_fifo_full] [get_bd_pins axis_addr_fifo_0/almost_full]
connect_bd_net -net axis_compl_fifo_0_almost_empty [get_bd_pins action_config_0/hbm_compl_fifo_empty] [get_bd_pins axis_compl_fifo_0/almost_empty]
@@ -708,8 +722,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
connect_bd_net -net network_stack_packets_udp [get_bd_pins action_config_0/packets_udp] [get_bd_pins network_stack/packets_udp]
connect_bd_net -net network_stack_packets_udp_ap_vld [get_bd_pins action_config_0/packets_udp_valid] [get_bd_pins network_stack/packets_udp_ap_vld]
connect_bd_net -net one_dout [get_bd_pins axi_datamover_0/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_0/m_axis_s2mm_sts_tready] [get_bd_pins axi_datamover_1/m_axis_mm2s_sts_tready] [get_bd_pins axi_datamover_1/m_axis_s2mm_sts_tready] [get_bd_pins one/dout]
connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_compl_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_10/s_axis_aresetn] [get_bd_pins axis_data_fifo_11/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_8/s_axis_aresetn] [get_bd_pins axis_data_fifo_9/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_3/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axis_broadcast_0/ap_rst_n] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
connect_bd_net -net reset_axi [get_bd_pins axi_rst_n] [get_bd_pins action_config_0/resetn] [get_bd_pins axis_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_adu_histo_result_fifo/s_axis_aresetn] [get_bd_pins axis_compl_fifo_0/s_axis_aresetn] [get_bd_pins axis_compl_fifo_1/s_axis_aresetn] [get_bd_pins axis_compl_fifo_2/s_axis_aresetn] [get_bd_pins axis_compl_fifo_3/s_axis_aresetn] [get_bd_pins axis_compl_fifo_4/s_axis_aresetn] [get_bd_pins axis_compl_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_10/s_axis_aresetn] [get_bd_pins axis_data_fifo_11/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_data_fifo_5/s_axis_aresetn] [get_bd_pins axis_data_fifo_6/s_axis_aresetn] [get_bd_pins axis_data_fifo_7/s_axis_aresetn] [get_bd_pins axis_data_fifo_8/s_axis_aresetn] [get_bd_pins axis_data_fifo_9/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_c2h_data/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_cmd/s_axis_aresetn] [get_bd_pins axis_data_fifo_h2c_data/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_cmd_fifo_3/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_0/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_1/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_2/s_axis_aresetn] [get_bd_pins axis_datamover_fifo_3/s_axis_aresetn] [get_bd_pins axis_eth_in_fifo/s_axis_aresetn] [get_bd_pins axis_frame_generator_fifo_0/s_axis_aresetn] [get_bd_pins axis_hbm_handles_fifo/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_0/s_axis_aresetn] [get_bd_pins axis_integration_result_fifo_1/s_axis_aresetn] [get_bd_pins axis_register_slice_0/aresetn] [get_bd_pins axis_register_slice_1/aresetn] [get_bd_pins axis_register_slice_data_in_0/aresetn] [get_bd_pins axis_register_slice_host_mem/aresetn] [get_bd_pins axis_register_slice_udp/aresetn] [get_bd_pins axis_udp_addr_fifo_0/s_axis_aresetn] [get_bd_pins axis_udp_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_completion_fifo_0/s_axis_aresetn] [get_bd_pins axis_work_request_fifo_0/s_axis_aresetn] [get_bd_pins network_stack/resetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins smartconnect_1/aresetn] [get_bd_pins smartconnect_2/aresetn]
connect_bd_net -net reset_hls [get_bd_pins ap_rst_n] [get_bd_pins adu_histo_0/ap_rst_n] [get_bd_pins axi_datamover_0/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axi_mm2s_aresetn] [get_bd_pins axi_datamover_1/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_1/m_axis_mm2s_cmdsts_aresetn] [get_bd_pins axi_datamover_1/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axis_256_to_512_0/ap_rst_n] [get_bd_pins axis_broadcast_0/ap_rst_n] [get_bd_pins data_collection_fsm_0/ap_rst_n] [get_bd_pins frame_generator_0/ap_rst_n] [get_bd_pins host_writer_0/ap_rst_n] [get_bd_pins integration_0/ap_rst_n] [get_bd_pins jf_conversion_0/ap_rst_n] [get_bd_pins load_calibration_0/ap_rst_n] [get_bd_pins load_from_hbm_0/ap_rst_n] [get_bd_pins mailbox_0/S0_AXI_ARESETN] [get_bd_pins mask_missing_0/ap_rst_n] [get_bd_pins network_stack/ap_rst_n] [get_bd_pins save_to_hbm_0/ap_rst_n] [get_bd_pins spot_finder_0/ap_rst_n] [get_bd_pins stream_merge_0/ap_rst_n] [get_bd_pins timer_hbm/ap_rst_n] [get_bd_pins timer_host/ap_rst_n]
connect_bd_net -net timer_hbm_counter [get_bd_pins action_config_0/stalls_hbm] [get_bd_pins timer_hbm/counter]
connect_bd_net -net timer_hbm_counter_ap_vld [get_bd_pins action_config_0/stalls_hbm_valid] [get_bd_pins timer_hbm/counter_ap_vld]
connect_bd_net -net timer_host_counter [get_bd_pins action_config_0/stalls_host] [get_bd_pins timer_host/counter]
receiver/AcquisitionDevice.h
+1 -1
View File
@@ -24,7 +24,7 @@ struct IntegrationResult {
int64_t count;
int64_t sum;
int64_t sum2;
int64_t reserved[5];
int64_t reserved;
};
class AcquisitionDevice {
receiver/HLSSimulatedDevice.cpp
+12 -5
View File
@@ -240,7 +240,8 @@ void HLSSimulatedDevice::HLSMainThread() {
hls::stream<ap_uint<16>> hbm_handles;
hls::stream<ap_uint<512>> adu_histo_result;
hls::stream<ap_uint<192>> integration_result;
hls::stream<ap_axiu<256,1,1,1>> integration_result_0;
hls::stream<ap_uint<512>> integration_result_1;
hls::stream<ap_uint<512>> spot_finder_result;
hls::stream<ap_uint<UDP_METADATA_STREAM_WIDTH> > udp_metadata;
@@ -350,15 +351,18 @@ void HLSSimulatedDevice::HLSMainThread() {
hls_cores.emplace_back([&] { spot_finder(converted_9, spot_finder_result);});
// 7. Integration of pixels
hls_cores.emplace_back([&] { integration(converted_6, converted_7, integration_result, compl4, compl5,
hls_cores.emplace_back([&] { integration(converted_6, converted_7, integration_result_0, compl4, compl5,
hbm.data(), hbm.data(), hbm_if_size);});
// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { axis_256_to_512(integration_result_0, integration_result_1);});
// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { timer_host(converted_7, converted_8, counter_host); });
// 8. Prepare data to write to host memory
hls_cores.emplace_back([&] {
host_writer(converted_8, adu_histo_result, integration_result, spot_finder_result,
host_writer(converted_8, adu_histo_result, integration_result_1, spot_finder_result,
compl5, datamover_out.GetDataStream(),
datamover_out.GetCtrlStream(), work_request_stream, completion_stream,
packets_processed, host_writer_idle, err_reg); });
@@ -426,7 +430,10 @@ void HLSSimulatedDevice::HLSMainThread() {
if (!hbm_handles.empty())
throw std::runtime_error("Handles queue not empty");
if (!integration_result.empty())
if (!integration_result_0.empty())
throw std::runtime_error("Integration result queue not empty");
if (!integration_result_1.empty())
throw std::runtime_error("Integration result queue not empty");
if (!datamover_in.GetDataStream().empty())