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c66c06e8f5
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FPGA: Fix setup action
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2023-11-02 15:09:04 +01:00 |
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8cd0d497ad
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FPGA: Allow saving 32-bit unsigned.
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2023-11-02 13:32:29 +01:00 |
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f21f226a59
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Move MAX_FPGA_SUMMATION to Definitions.h
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2023-11-02 12:55:52 +01:00 |
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b3eceef7cd
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FPGA: Max module number is 32
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2023-11-01 15:55:06 +01:00 |
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9f110f3c1a
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FPGA: nmodules is actually module - 1 (there will be never 0 modules, while it can encode 32)
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2023-11-01 14:28:32 +01:00 |
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112a62fc7f
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FPGA: remove limit of modules for frame_generator
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2023-11-01 14:20:43 +01:00 |
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8f2b01be80
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FPGA: frame_generator and load_calibration return value for error checking
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2023-11-01 13:31:41 +01:00 |
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a71121482e
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FPGAIntegrationTest: More parameters in packet generator custom frame test
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2023-11-01 13:29:06 +01:00 |
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31304553be
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FPGA: sls_detector had hardcoded max module number -> fixed
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2023-11-01 13:28:17 +01:00 |
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3940f067a8
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MAX_MODULES_FPGA moved to Definitions.h => This needs to be const for RELEASE_LEVEL
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2023-11-01 13:16:22 +01:00 |
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b84febed5c
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FPGA: Update max summation to 128
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2023-11-01 12:23:25 +01:00 |
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a17b75862e
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Update CI scripts. Remove retaining .bit files (large and not useful) and remove RHEL7 specific parts.
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2023-11-01 12:18:37 +01:00 |
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e0ef39a9ec
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Update README.md
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2023-11-01 12:18:37 +01:00 |
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f9ac919e3c
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Merge branch 'fpga_multipixel' into 'main'
FPGA: Add capability for auto-summation and image processing to the FPGA
See merge request jungfraujoch/nextgendcu!9
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2023-10-29 11:29:46 +01:00 |
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05a35855eb
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Extend frame summation to 64
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2023-10-28 17:07:22 +02:00 |
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270dd1224b
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Receiver: remove JF conversion on CPU
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2023-10-28 17:00:04 +02:00 |
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c8862c8aa6
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Receiver: remove Mellanox device and Linux socket (both are much less functional as compared to FPGA)
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2023-10-28 16:50:55 +02:00 |
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2ed91c1849
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FPGA: transfer for image and processing results are separate DMA transactions
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2023-10-28 16:47:06 +02:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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fbc4f79a40
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FPGA: Frame_summation operates internally on 24-bit integers
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2023-10-28 06:22:06 +02:00 |
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4fbd747341
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FPGA: Remove multipixel from the pipeline
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2023-10-27 20:47:44 +02:00 |
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d562a4b435
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FPGA driver: Remove TODO for sysfs from README
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2023-10-27 19:51:59 +02:00 |
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28673ffc63
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Merge branch 'pcie_driver_sysfs' into 'main'
PCIe driver: Added sysfs bindings
See merge request jungfraujoch/nextgendcu!8
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2023-10-27 19:49:47 +02:00 |
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673e0f610a
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FPGA driver: Read MAC address from CMS on card initialization
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2023-10-27 19:48:40 +02:00 |
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4978149fdd
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FPGA: Add register slice in the data pipeline
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2023-10-27 19:43:40 +02:00 |
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c896ec5659
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FPGA: Remove bitshuffle from the pipeline
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2023-10-27 19:41:02 +02:00 |
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f46a8e47a0
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FPGA: Use AggressiveExplore for routing
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2023-10-27 19:12:27 +02:00 |
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817d541fb0
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HLS: save_to_hbm.cpp send frames in proper order
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2023-10-27 16:02:23 +02:00 |
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08c2427fc7
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FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign
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2023-10-27 15:42:24 +02:00 |
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e06086e956
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HLSSimulatedDevice: Change order integration -> frame_summation -> spot finding
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2023-10-27 15:41:09 +02:00 |
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b08071887b
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HLSSimulatedDevice: Add frame_summation
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2023-10-27 15:36:19 +02:00 |
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700d5b25af
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HLSSimulatedDevice: Add frame_summation_reoder_compl
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2023-10-27 15:33:29 +02:00 |
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3b802effa8
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HLSSimulatedDevice: Remove module_upside_down
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2023-10-27 15:28:49 +02:00 |
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7973c2ca81
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HLS: Minor fixes to adu_histo.cpp
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2023-10-27 15:27:36 +02:00 |
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4fbac629d6
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HLS: Use U55C part number for proper usage statistics
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2023-10-27 13:54:35 +02:00 |
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b022dd0055
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Improved FPGA README.md
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2023-10-27 12:24:50 +02:00 |
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cf69aef472
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FPGA: Add extra register slices for upside_down
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2023-10-26 22:36:08 +02:00 |
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2268486824
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HLS: Added frame_summation core
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2023-10-26 22:31:09 +02:00 |
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4011c4541d
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HLS: frames inside HLS logic are counted from 0, even if JUNGFRAU counts them from 1
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2023-10-26 19:42:15 +02:00 |
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473bf17ae7
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HLS: axis_completion has extra parameter (ignore) that makes the frame ignored by load_from_hbm, but HBM handle is still recovered
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2023-10-26 18:14:35 +02:00 |
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efac89f89e
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FPGAIntegrationTest: Add invert and bitshuffle tests
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2023-10-25 22:37:25 +02:00 |
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7df76a5c76
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FPGAAcquisitionDevice: add option to customize execution flags
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2023-10-25 22:28:13 +02:00 |
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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439d6fa12a
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FPGA: Spot finder won't use multipixels for mean/variance calculation
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2023-10-25 18:18:29 +02:00 |
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6bcf54f603
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FPGA: Add bitshuffle to the design (warning! no test for full integration!)
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2023-10-25 11:07:21 +02:00 |
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a611d3f08b
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FPGA: Adapt host writer to multipixel core. (TODO -> multipixels should be masked for rad. int. and spot finding)
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2023-10-24 19:11:23 +02:00 |
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d408b3ed2a
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FPGA: Integrate add multipixel into the design
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2023-10-24 18:58:59 +02:00 |
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b33e996569
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FPGA: Add multipixel - add test.
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2023-10-24 18:05:59 +02:00 |
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c37a9fa768
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FPGA: Add multipixel - handle division by 2 and 4 for multipixels.
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2023-10-24 18:05:48 +02:00 |
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e195432aea
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RawToConvertedGeometry: Separate core functions that require minimum headers
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2023-10-24 17:54:14 +02:00 |
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