FPGA: sls_detector had hardcoded max module number -> fixed

2023-11-01 13:28:17 +01:00
parent 3940f067a8
commit 31304553be
1 changed files with 1 additions and 1 deletions
@@ -76,7 +76,7 @@ void sls_detector(AXI_STREAM &udp_payload_in,
                    addr.debug = packet_in.data(5 * 64 + 31, 5 * 64);
                    addr.timestamp = packet_in.data(3 * 64 + 63, 3 * 64);
                    addr.bunchid = packet_in.data(2 * 64 + 63, 2 * 64);
-                    addr.module = (column % 32) / 2;
+                    addr.module = (column / 2) % MAX_MODULES_FPGA;
                    addr.eth_packet = (packet_in.data(127, 96) % 128) | (module_part * 64);
                    addr.exptime = packet_in.data(95, 64);
                    addr.last = 0;