From 31304553bed7444e59b1e8997208df97120fccc3 Mon Sep 17 00:00:00 2001
From: Filip Leonarski <filip.leonarski@psi.ch>
Date: Wed, 1 Nov 2023 13:28:17 +0100
Subject: [PATCH] FPGA: sls_detector had hardcoded max module number -> fixed

---
 fpga/hls/sls_detector.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga/hls/sls_detector.cpp b/fpga/hls/sls_detector.cpp
index 5ee88d87..a050e67a 100644
--- a/fpga/hls/sls_detector.cpp
+++ b/fpga/hls/sls_detector.cpp
@@ -76,7 +76,7 @@ void sls_detector(AXI_STREAM &udp_payload_in,
                     addr.debug = packet_in.data(5 * 64 + 31, 5 * 64);
                     addr.timestamp = packet_in.data(3 * 64 + 63, 3 * 64);
                     addr.bunchid = packet_in.data(2 * 64 + 63, 2 * 64);
-                    addr.module = (column % 32) / 2;
+                    addr.module = (column / 2) % MAX_MODULES_FPGA;
                     addr.eth_packet = (packet_in.data(127, 96) % 128) | (module_part * 64);
                     addr.exptime = packet_in.data(95, 64);
                     addr.last = 0;