FPGA: remove limit of modules for frame_generator

This commit is contained in:
2023-11-01 14:20:43 +01:00
parent 8f2b01be80
commit 112a62fc7f
10 changed files with 62 additions and 39 deletions

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@@ -134,7 +134,6 @@
#define FPGA_INTEGRATION_BIN_COUNT 1024
#define MAX_MODULES_FPGA 16
#define FRAME_GENERATOR_MODULES (MAX_MODULES_FPGA)
#define ADU_HISTO_BIN_WIDTH 32
#define ADU_HISTO_BIN_COUNT (65536/ ADU_HISTO_BIN_WIDTH)

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@@ -58,8 +58,8 @@ void generate_packet(STREAM_512 &data_out,
ap_uint<208> remainder = header(719, 512);
for (int i = 0; i < 128; i++) {
ap_uint<512> tmp;
tmp(255, 0) = d_hbm_p0[offset_hbm_0 + (module % FRAME_GENERATOR_MODULES) * 128 * 128 + eth_packet * 128 + i];
tmp(511, 256) = d_hbm_p1[offset_hbm_1 + (module % FRAME_GENERATOR_MODULES) * 128 * 128 + eth_packet * 128 + i];
tmp(255, 0) = d_hbm_p0[offset_hbm_0 + module * 128 * 128 + eth_packet * 128 + i];
tmp(511, 256) = d_hbm_p1[offset_hbm_1 + module * 128 * 128 + eth_packet * 128 + i];
packet.data(207, 0) = remainder;
packet.data(511, 208) = tmp(303, 0);

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@@ -73,8 +73,6 @@
#define ADDR_CMS_HBM_TEMP1_INS_REG 0x028268 // in C
#define ADDR_CMS_HBM_TEMP2_INS_REG 0x0282BC // in C
#define INT_PKT_GEN_FRAME_SIZE_BYTES (FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE*sizeof(short))
struct jfjoch_buf {
dma_addr_t dma_address;
void *kernel_address;

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@@ -98,26 +98,50 @@ void FPGAAcquisitionDevice::InitializeIntegrationMap(const DiffractionExperiment
HW_LoadIntegrationMap(modules);
}
void FPGAAcquisitionDevice::SetInternalGeneratorFrame(const std::vector<uint16_t> &v) {
if (v.size() == RAW_MODULE_SIZE) {
for (int m = 0; m < FRAME_GENERATOR_MODULES; m++) {
memcpy(internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE,
v.data(), RAW_MODULE_SIZE * sizeof(uint16_t));
}
} else if (v.size() == RAW_MODULE_SIZE * FRAME_GENERATOR_MODULES) {
memcpy(internal_pkt_gen_frame.data(), v.data(), FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE * sizeof(uint16_t));
} else
void FPGAAcquisitionDevice::SetInternalGeneratorFrameForAllModules(const std::vector<uint16_t> &v) {
if (v.size() != RAW_MODULE_SIZE) {
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Error in size of custom internal generator frame");
}
if (FRAME_GENERATOR_MODULES > buffer_device.size())
for (int m = 0; m < max_modules; m++) {
memcpy(internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE,
v.data(), RAW_MODULE_SIZE * sizeof(uint16_t));
}
if (max_modules > buffer_device.size())
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Not enough host/FPGA buffers to load all integration map values");
for (int m = 0; m < FRAME_GENERATOR_MODULES; m++)
for (int m = 0; m < max_modules; m++)
memcpy(buffer_device[m], internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE, RAW_MODULE_SIZE * sizeof(uint16_t));
HW_LoadInternalGeneratorFrame(FRAME_GENERATOR_MODULES);
HW_LoadInternalGeneratorFrame(max_modules);
}
void FPGAAcquisitionDevice::SetInternalGeneratorFrame(const std::vector<uint16_t> &v) {
if (v.empty() || (v.size() % RAW_MODULE_SIZE != 0)) {
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Error in size of custom internal generator frame");
}
size_t nmodules = v.size() / RAW_MODULE_SIZE;
if (nmodules > max_modules) {
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Max number of modules exceeded");
}
memcpy(internal_pkt_gen_frame.data(), v.data(), nmodules * RAW_MODULE_SIZE * sizeof(uint16_t));
if (nmodules > buffer_device.size())
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Not enough host/FPGA buffers to load all integration map values");
for (int m = 0; m < nmodules; m++)
memcpy(buffer_device[m], internal_pkt_gen_frame.data() + m * RAW_MODULE_SIZE, RAW_MODULE_SIZE * sizeof(uint16_t));
HW_LoadInternalGeneratorFrame(nmodules);
}
void FPGAAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &experiment, const JFCalibration &calib) {
@@ -329,12 +353,12 @@ void FPGAAcquisitionDevice::SetInternalGeneratorFrame() {
std::vector<uint16_t> tmp(RAW_MODULE_SIZE);
for (int i = 0; i < RAW_MODULE_SIZE; i++)
tmp[i] = i % 65536;
SetInternalGeneratorFrame(tmp);
SetInternalGeneratorFrameForAllModules(tmp);
}
FPGAAcquisitionDevice::FPGAAcquisitionDevice(uint16_t data_stream)
: AcquisitionDevice(data_stream),
internal_pkt_gen_frame(RAW_MODULE_SIZE * FRAME_GENERATOR_MODULES) {
internal_pkt_gen_frame(RAW_MODULE_SIZE * MAX_MODULES_FPGA) {
}
void FPGAAcquisitionDevice::SetSpotFinderParameters(int16_t count_threshold, double snr_threshold) {

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@@ -50,6 +50,7 @@ public:
const std::vector<float> &weights) override;
void SetInternalGeneratorFrame(const std::vector<uint16_t> &v);
void SetInternalGeneratorFrameForAllModules(const std::vector<uint16_t> &v);
void SetInternalGeneratorFrame();
std::vector<uint16_t> GetInternalGeneratorFrame() const override;
void SetSpotFinderParameters(int16_t count_threshold, double snr_threshold) override;

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@@ -93,14 +93,14 @@ bool JFJochReceiverTest(JFJochProtoBuf::ReceiverOutput &output, Logger &logger,
for (int i = 0; i < x.GetDataStreamsNum(); i++) {
uint32_t module0 = x.GetFirstModuleOfDataStream(i);
auto int_gen_frame = aq_devices[i]->GetInternalGeneratorFrame();
if (int_gen_frame.size() != FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE) {
if (int_gen_frame.size() < x.GetModulesNum(i) * RAW_MODULE_SIZE) {
logger.Error("Wrong internal generator frame size");
return false;
}
for (int m = 0; m < x.GetModulesNum(i); m++) {
memcpy(raw_expected_image.data() + (module0 + m) * RAW_MODULE_SIZE,
int_gen_frame.data() + (m % FRAME_GENERATOR_MODULES) * RAW_MODULE_SIZE,
int_gen_frame.data() + m * RAW_MODULE_SIZE,
RAW_MODULE_SIZE * sizeof(uint16_t));
}
}

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@@ -35,13 +35,14 @@ void MockAcquisitionDevice::Cancel() {
MockAcquisitionDevice::MockAcquisitionDevice(uint16_t data_stream, size_t in_frame_buffer_size_modules,
int16_t in_numa_node)
: AcquisitionDevice(data_stream), internal_pkt_gen_frame(FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE),
internal_pkt_gen_frame_conv(FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE) {
max_modules = 16;
: AcquisitionDevice(data_stream) {
max_modules = MAX_MODULES_FPGA;
internal_pkt_gen_frame.resize(max_modules * RAW_MODULE_SIZE);
internal_pkt_gen_frame_conv.resize(max_modules * RAW_MODULE_SIZE);
MapBuffersStandard(in_frame_buffer_size_modules, 1, in_numa_node);
max_handle = in_frame_buffer_size_modules;
for (int i = 0; i < FRAME_GENERATOR_MODULES * RAW_MODULE_SIZE; i++) {
for (int i = 0; i < max_modules * RAW_MODULE_SIZE; i++) {
internal_pkt_gen_frame[i] = i % 65536;
internal_pkt_gen_frame_conv[i] = i % 65536;
}
@@ -153,7 +154,7 @@ void MockAcquisitionDevice::SetCustomInternalGeneratorFrame(const std::vector<ui
if (v.size() != RAW_MODULE_SIZE)
throw JFJochException(JFJochExceptionCategory::InputParameterInvalid,
"Error in size of custom internal generator frame");
for (int m = 0; m < FRAME_GENERATOR_MODULES ; m++) {
for (int m = 0; m < max_modules ; m++) {
memcpy(internal_pkt_gen_frame.data() + RAW_MODULE_SIZE * m,
v.data(),
RAW_MODULE_SIZE);
@@ -164,7 +165,7 @@ void MockAcquisitionDevice::SetCustomInternalGeneratorFrame(const std::vector<ui
}
void MockAcquisitionDevice::InitializeCalibration(const DiffractionExperiment &experiment, const JFCalibration &calib) {
for (int m = 0; (m < experiment.GetModulesNum(data_stream)) && (m < FRAME_GENERATOR_MODULES); m++) {
for (int m = 0; (m < experiment.GetModulesNum(data_stream)) && (m < max_modules); m++) {
JFConversionFloatingPoint conv;
conv.Setup(calib.GainCalibration(experiment.GetFirstModuleOfDataStream(data_stream) + m),
calib.Pedestal(experiment.GetFirstModuleOfDataStream(data_stream) + m,0),

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@@ -152,7 +152,7 @@ int main(int argc, char **argv) {
for (int i = 0; i < nstreams; i++) {
pcie_devices.push_back(std::make_unique<PCIExpressDevice>(dev_name[i], i));
pcie_devices[i]->SetInternalGeneratorFrame(input);
pcie_devices[i]->SetInternalGeneratorFrameForAllModules(input);
pcie_devices[i]->EnableLogging(&logger);
pcie_devices[i]->SetDefaultMAC();
pcie_devices[i]->SetIPv4Address((i << 24) + 0x010a0a0a);

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@@ -44,7 +44,7 @@ AcquisitionDevice *SetupAcquisitionDevice(const nlohmann::json &input, uint16_t
auto filename = input["custom_test_frame"].get<std::string>();
std::fstream file(filename.c_str(), std::fstream::in | std::fstream::binary);
file.read((char *) tmp.data(), RAW_MODULE_SIZE * sizeof(uint16_t));
pci_dev->SetInternalGeneratorFrame(tmp);
pci_dev->SetInternalGeneratorFrameForAllModules(tmp);
}
ret = pci_dev;
}

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@@ -44,7 +44,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Ful
const size_t nframes = 2;
DiffractionExperiment x((DetectorGeometry(nmodules)));
std::vector<uint16_t> test_frame(FRAME_GENERATOR_MODULES*RAW_MODULE_SIZE);
std::vector<uint16_t> test_frame(nmodules*RAW_MODULE_SIZE);
std::mt19937 g1(1387);
std::uniform_int_distribution<uint16_t> dist(0, 65535);
@@ -73,7 +73,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Ful
auto imageBuf = (uint16_t *) test.GetDeviceOutput(image, m)->pixels;
for (int i = 0; i < RAW_MODULE_SIZE; i++) {
REQUIRE(imageBuf[i] == test_frame[(m % FRAME_GENERATOR_MODULES) * RAW_MODULE_SIZE + i]);
REQUIRE(imageBuf[i] == test_frame[m * RAW_MODULE_SIZE + i]);
}
}
}
@@ -543,7 +543,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_apply_pixel_mask", "[FPGA]
HLSSimulatedDevice test(0, 64);
test.SetInternalGeneratorFrame(test_frame);
test.SetInternalGeneratorFrameForAllModules(test_frame);
REQUIRE_NOTHROW(test.InitializeCalibration(x, c));
REQUIRE_NOTHROW(test.StartAction(x));
@@ -919,7 +919,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_15_storage_cell_convert_G0
std::vector<uint16_t> data(RAW_MODULE_SIZE);
for (auto &i: data)
i = 16000;
REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data));
REQUIRE_NOTHROW(test.SetInternalGeneratorFrameForAllModules(data));
JFCalibration c(x);
for (int i = 0; i < nstoragecells; i++) {
@@ -967,7 +967,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_8_storage_cell_convert_G0"
std::vector<uint16_t> data(RAW_MODULE_SIZE);
for (auto &i: data)
i = 16000;
REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data));
REQUIRE_NOTHROW(test.SetInternalGeneratorFrameForAllModules(data));
JFCalibration c(x);
for (int i = 0; i < nstoragecells; i++) {
@@ -1015,7 +1015,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_16_storage_cell_convert_G0
std::vector<uint16_t> data(RAW_MODULE_SIZE);
for (auto &i: data)
i = 16000;
REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data));
REQUIRE_NOTHROW(test.SetInternalGeneratorFrameForAllModules(data));
JFCalibration c(x);
for (int i = 0; i < nstoragecells; i++) {
@@ -1055,7 +1055,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_storage_cell_convert_G1",
std::vector<uint16_t> data(RAW_MODULE_SIZE);
for (auto &i: data)
i = 16384 | 10;
REQUIRE_NOTHROW(test.SetInternalGeneratorFrame(data));
REQUIRE_NOTHROW(test.SetInternalGeneratorFrameForAllModules(data));
JFCalibration c(x);
for (int i = 0; i < 16; i++) {
@@ -1102,7 +1102,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_integration", "[FPGA][Full
for (int i = 2; i < RAW_MODULE_SIZE; i++)
frame[i] = 32754;
test.SetInternalGeneratorFrame(frame);
test.SetInternalGeneratorFrameForAllModules(frame);
std::vector<uint16_t> integration_map(nmodules * RAW_MODULE_SIZE, 54);
for (int i = 0; i < RAW_MODULE_SIZE/2; i++) {
@@ -1163,7 +1163,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_count_threshol
frame [ 89*1024 + 300] = 8;
frame [300*1024 + 0] = 9;
test.SetInternalGeneratorFrame(frame);
test.SetInternalGeneratorFrameForAllModules(frame);
test.SetSpotFinderParameters(10, 0.0);
@@ -1212,7 +1212,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_snr_threshold"
frame [ 89*1024 + 300] = 7;
frame [300*1024 + 0] = 3;
test.SetInternalGeneratorFrame(frame);
test.SetInternalGeneratorFrameForAllModules(frame);
test.SetSpotFinderParameters(0, 10);