FPGA: Adapt host writer to multipixel core. (TODO -> multipixels should be masked for rad. int. and spot finding)

fpga/hls/host_writer.cpp

@@ -116,7 +116,7 @@ void host_writer(STREAM_512 &data_in,
 
     ap_uint<32> data_collection_mode = ACT_REG_MODE(packet.data);
     ap_uint<32> data_collection_id = data_collection_mode(31, 16);
-
+    ap_uint<1> add_multipixel_mode = (data_collection_mode & MODE_ADD_MULTIPIXEL) ? 1 : 0;
     uint64_t internal_packets_processed = 0;
     packets_processed = internal_packets_processed;
 
@@ -128,11 +128,6 @@ void host_writer(STREAM_512 &data_in,
     s_axis_completion >> cmpl;
     while (!cmpl.last) {
         read_request(s_axis_work_request, req_handle, req_host_offset);
-        setup_datamover(datamover_out_cmd, req_host_offset,
-                        RAW_MODULE_SIZE * sizeof(uint16_t) * (16 + 1) / 16
-                        + 64
-                        + (FPGA_INTEGRATION_BIN_COUNT/4)*64
-                        + ADU_HISTO_BIN_COUNT / 16 * 64);
 
         packet_512_t packet_out;
         packet_out.strb = UINT64_MAX;
@@ -142,12 +137,24 @@ void host_writer(STREAM_512 &data_in,
         packet_out.id = 0;
         packet_out.last = 0;
 
-        for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
+        setup_datamover(datamover_out_cmd, req_host_offset,
+                        257 * 64 * 32 * sizeof(uint16_t)
+                        + RAW_MODULE_SIZE * sizeof(uint16_t) / 16
+                        + 64
+                        + (FPGA_INTEGRATION_BIN_COUNT / 4) * 64
+                        + ADU_HISTO_BIN_COUNT / 16 * 64);
+
+
+            for (int i = 0; i < 257 * 64 * 32 * sizeof(uint16_t) / 64; i++) {
 #pragma HLS PIPELINE II=1
-            data_in >> packet;
-            packet_out.data = packet.data;
-            host_memory_out << packet_out;
-        }
+                if (add_multipixel_mode || (i < 256 * 64 * 32 * sizeof(uint16_t) / 64)) {
+                    data_in >> packet;
+                    packet_out.data = packet.data;
+                } else
+                    packet_out.data = 0;
+                host_memory_out << packet_out;
+            }
+
 
         for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / (64 * 16) + 1; i++) {
 #pragma HLS PIPELINE II=1

receiver/AcquisitionDevice.h

@@ -37,7 +37,7 @@ struct SpotFindingResult {
 };
 
 struct DeviceOutput {
-    int16_t pixels[RAW_MODULE_SIZE];
+    int16_t pixels[257 * 64 * 32];
     SpotFindingResult spot_finding_result;
     IntegrationResult integration_result[FPGA_INTEGRATION_BIN_COUNT];
     uint32_t adu_histogram[ADU_HISTO_BIN_COUNT];