FPGA: transfer for image and processing results are separate DMA transactions

fpga/hls/host_writer.cpp

@@ -139,34 +139,38 @@ void host_writer(STREAM_512 &data_in,
 
 
         if (mode_32bit) {
-            setup_datamover(datamover_out_cmd, req_host_offset,
-                            512 * 64 * 32 * sizeof(uint16_t)
-                            + RAW_MODULE_SIZE * sizeof(uint16_t) / 16
-                            + 64
-                            + (FPGA_INTEGRATION_BIN_COUNT / 4) * 64
-                            + ADU_HISTO_BIN_COUNT / 16 * 64);
+            setup_datamover(datamover_out_cmd, req_host_offset, 512 * 64 * 32 * sizeof(uint16_t));
             for (int i = 0; i < 512 * 64 * 32 * sizeof(uint16_t) / 64; i++) {
 #pragma HLS PIPELINE II=1
                 data_in >> packet;
                 packet_out.data = packet.data;
+                if (i == 512 * 64 * 32 * sizeof(uint16_t) / 64 - 1)
+                    packet_out.last = 1;
+                else
+                    packet_out.last = 0;
                 host_memory_out << packet_out;
             }
         } else {
-            setup_datamover(datamover_out_cmd, req_host_offset,
-                            256 * 64 * 32 * sizeof(uint16_t)
-                            + RAW_MODULE_SIZE * sizeof(uint16_t) / 16
-                            + 64
-                            + (FPGA_INTEGRATION_BIN_COUNT / 4) * 64
-                            + ADU_HISTO_BIN_COUNT / 16 * 64);
+            setup_datamover(datamover_out_cmd, req_host_offset, 256 * 64 * 32 * sizeof(uint16_t));
 
             for (int i = 0; i < 256 * 64 * 32 * sizeof(uint16_t) / 64; i++) {
 #pragma HLS PIPELINE II=1
                 data_in >> packet;
                 packet_out.data = packet.data;
+                if (i == 256 * 64 * 32 * sizeof(uint16_t) / 64 - 1)
+                    packet_out.last = 1;
+                else
+                    packet_out.last = 0;
                 host_memory_out << packet_out;
             }
         }
 
+        packet_out.last = 0;
+
+        setup_datamover(datamover_out_cmd, req_host_offset + 512 * 64 * 32 * sizeof(uint16_t),
+                        RAW_MODULE_SIZE * sizeof(uint16_t) / 16 + 64
+                        + (FPGA_INTEGRATION_BIN_COUNT / 4) * 64
+                        + ADU_HISTO_BIN_COUNT / 16 * 64);
 
         for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / (64 * 16) + 1; i++) {
 #pragma HLS PIPELINE II=1

receiver/AcquisitionDevice.cpp

@@ -87,7 +87,7 @@ void AcquisitionDevice::WaitForActionComplete() {
 
     while (c.type != Completion::Type::End) {
         work_completion_count++;
-        while (work_completion_count > GetCompletedDescriptors())
+        while (2 * work_completion_count > GetCompletedDescriptors()) // Two descriptors per module
             std::this_thread::sleep_for(std::chrono::milliseconds(1));
 
         if (c.frame_number >= expected_frames) {

receiver/AcquisitionDevice.h

@@ -37,7 +37,7 @@ struct SpotFindingResult {
 };
 
 struct DeviceOutput {
-    int16_t pixels[256 * 64 * 32];
+    int16_t pixels[512 * 64 * 32];
     SpotFindingResult spot_finding_result;
     IntegrationResult integration_result[FPGA_INTEGRATION_BIN_COUNT];
     uint32_t adu_histogram[ADU_HISTO_BIN_COUNT];

receiver/LinuxSocketDevice.cpp

@@ -137,5 +137,5 @@ void LinuxSocketDevice::FindMACAddress() {
 }
 
 uint32_t LinuxSocketDevice::GetCompletedDescriptors() const {
-    return completed_descriptors;
+    return completed_descriptors * 2;
 }

receiver/MlxRawEthDevice.cpp

@@ -169,7 +169,7 @@ void MlxRawEthDevice::SendARP(IBRegBuffer &buffer, IBQueuePair &qp) {
 }
 
 uint32_t MlxRawEthDevice::GetCompletedDescriptors() const {
-    return completed_descriptors;
+    return completed_descriptors * 2;
 }
 
 #endif //JFJOCH_USE_IBVERBS

receiver/MockAcquisitionDevice.cpp

@@ -182,5 +182,5 @@ std::vector<uint16_t> MockAcquisitionDevice::GetInternalGeneratorFrame() const {
 }
 
 uint32_t MockAcquisitionDevice::GetCompletedDescriptors() const {
-    return completed_descriptors;
+    return completed_descriptors * 2;
 }

tests/FPGAIntegrationTest.cpp

@@ -36,7 +36,7 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator", "[FPGA][Full]") {
                 REQUIRE(imageBuf[i] == i % 65536);
         }
     }
-    REQUIRE(test.GetCompletedDescriptors() == (4 + DELAY_FRAMES_STOP_AND_QUIT - 1) * nmodules);
+    REQUIRE(test.GetCompletedDescriptors() == 2 * (4 + DELAY_FRAMES_STOP_AND_QUIT - 1) * nmodules);
 }
 
 TEST_CASE("HLS_C_Simulation_internal_packet_generator_custom_frame", "[FPGA][Full]") {