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HLSSimulatedDevice: Remove module_upside_down

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This commit is contained in:
leonarski_f
2023-10-27 15:28:49 +02:00
parent 7973c2ca81
commit 3b802effa8
2 changed files with 1 additions and 48 deletions
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5
receiver/HLSSimulatedDevice.cpp
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@@ -361,11 +361,8 @@ void HLSSimulatedDevice::HLSMainThread() {
hls_cores.emplace_back([&] { axis_128_to_512(integration_result_0, integration_result_1);});
// 8. Invert module upside down
hls_cores.emplace_back([&] { module_upside_down(converted_7, converted_8);});
// 9. Extend multipixels
hls_cores.emplace_back([&] { add_multipixel(converted_8, converted_9);});
hls_cores.emplace_back([&] { add_multipixel(converted_7, converted_9);});
// 10. Apply bitshuffle
hls_cores.emplace_back([&] { bitshuffle(converted_9, converted_10);});

44
tests/FPGAIntegrationTest.cpp
View File

@@ -1236,50 +1236,6 @@ TEST_CASE("HLS_C_Simulation_internal_packet_generator_spot_finder_snr_threshold"
REQUIRE (spot_finder_result.strong_pixel[(89*1024 + 300) / 8] == (1<<4)); // 300 % 8 == 4
}
TEST_CASE("HLS_C_Simulation_upside_down", "[FPGA][Full]") {
const uint16_t nmodules = 4;
DiffractionExperiment x((DetectorGeometry(nmodules)));
std::vector<uint16_t> input_frame(FRAME_GENERATOR_MODULES*RAW_MODULE_SIZE);
std::vector<uint16_t> input_frame_transformed(FRAME_GENERATOR_MODULES*RAW_MODULE_SIZE);
std::mt19937 g1(1387);
std::uniform_int_distribution<uint16_t> dist(0, 65535);
for (int n = 0; n < nmodules; n++) {
for (int line = 0; line < RAW_MODULE_LINES; line++) {
size_t line_transformed = RAW_MODULE_LINES - 1 - line;
for (int col = 0; col < RAW_MODULE_COLS; col++) {
uint16_t tmp = dist(g1);
input_frame[n * RAW_MODULE_SIZE + line * RAW_MODULE_COLS + col] = tmp;
input_frame_transformed[n * RAW_MODULE_SIZE + line_transformed * RAW_MODULE_COLS + col] = tmp;
}
}
}
x.Mode(DetectorMode::Raw);
x.UseInternalPacketGenerator(true).ImagesPerTrigger(4).PedestalG0Frames(0);
HLSSimulatedDevice test(0, 64);
test.SetInternalGeneratorFrame(input_frame);
REQUIRE_NOTHROW(test.StartAction(x, MODE_MODULE_UPSIDE_DOWN));
REQUIRE_NOTHROW(test.WaitForActionComplete());
REQUIRE(test.OutputStream().size() == 1);
REQUIRE(test.GetBytesReceived() == 128 * nmodules * 4 * JUNGFRAU_PACKET_SIZE_BYTES);
for (int image = 0; image < 4; image++) {
for (int m = 0; m < nmodules; m++) {
auto imageBuf = (uint16_t *) test.GetDeviceOutput(image, m)->pixels;
for (int i = 0; i < RAW_MODULE_SIZE; i++) {
REQUIRE(imageBuf[i] == input_frame_transformed[m * RAW_MODULE_SIZE + i]);
}
}
}
}
TEST_CASE("HLS_C_Simulation_bitsuffle", "[FPGA][Full]") {
const uint16_t nmodules = 4;