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3b802effa8
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HLSSimulatedDevice: Remove module_upside_down
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2023-10-27 15:28:49 +02:00 |
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2268486824
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HLS: Added frame_summation core
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2023-10-26 22:31:09 +02:00 |
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4e60bb2f9e
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FPGA: Add option to invert modules upside down
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2023-10-25 22:20:45 +02:00 |
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6bcf54f603
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FPGA: Add bitshuffle to the design (warning! no test for full integration!)
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2023-10-25 11:07:21 +02:00 |
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d408b3ed2a
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FPGA: Integrate add multipixel into the design
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2023-10-24 18:58:59 +02:00 |
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3b65e6bf88
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FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5)
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2023-10-21 15:37:46 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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6691b01265
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PCIe driver: accept spot finding parameters
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2023-10-18 21:23:41 +02:00 |
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6565619035
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parallel_stream.h: Depth can be provided as template parameter to hls::stream (like in Vitis HLS)
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2023-10-18 12:10:00 +02:00 |
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05338887a7
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FPGA: Spot finder accepts 16-bit number for strong pixel threshold
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2023-10-16 22:07:41 +02:00 |
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faca7a3f15
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PCIe driver: Clean-up + add intermediate library between driver and AcquisitionDevice
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2023-10-16 19:54:13 +02:00 |
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c5ca10792e
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FPGA: Clean-up of spot_finder core + update README.MD
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2023-10-16 15:13:47 +02:00 |
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7889f1666a
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FPGA: Spot finder 2nd version improved
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2023-10-04 12:12:43 +02:00 |
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c6afbebd13
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FPGA: add old spot finder to the design (work in progress! - seems very high resource utilization + it is offset from proper result)
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2023-10-02 22:34:49 +02:00 |
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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5bb92aed61
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FPGA: Modify HLS for jf_conversion, so it is running after HBM buffer
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2023-09-29 14:44:08 +02:00 |
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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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0f7c14c267
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FPGA: integration calculates sum^2
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2023-09-25 22:23:06 +02:00 |
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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df0b0d8b96
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FPGA: add spot finder to the design
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2023-09-24 19:04:58 +02:00 |
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a70e3cf444
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FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis
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2023-09-22 21:49:41 +02:00 |
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5cf0d30603
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AcquisitionDevice: Enable access to integration results
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2023-09-22 20:32:13 +02:00 |
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f06e92fd1b
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FPGA: load_calibration allows to upload integration map
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2023-09-22 18:28:35 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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8e0edab0ee
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AcquisitionDevice: Count completed descriptors
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2023-09-19 12:53:59 +02:00 |
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86123eb2fe
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FPGA: Use datamover for save_to_hbm and load_from_hbm
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2023-09-19 07:36:56 +02:00 |
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a94bdacea9
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Revert "FPGA: use 4 HBM interfaces for load and save to HBM"
This reverts commit 28a29ea3183a35d8ba0dda0628ac727f8bfe4f17.
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2023-09-19 07:36:56 +02:00 |
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1fe5c474ee
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FPGA: use 4 HBM interfaces for load and save to HBM
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2023-09-19 07:36:56 +02:00 |
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2982097b8c
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FPGA: Use HBM as intermediary cache for images
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2023-09-19 07:36:56 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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362eb62d4b
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FPGA: Use own function to merge streams instead of AXI-Switch + more FIFO status saved
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2023-09-14 23:58:17 +02:00 |
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0b95456d3d
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Adapt PCIe driver and tests for the new frame generator
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2023-09-13 21:44:20 +02:00 |
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496d016c31
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FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets)
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2023-09-13 20:06:09 +02:00 |
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9d01630cfc
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FPGA: load calibration works as dedicated function of the card
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2023-09-12 14:34:42 +02:00 |
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8c3a25a8ad
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FPGA: load calibration operates directly on HBM
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2023-09-11 21:47:29 +02:00 |
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05000bab1f
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FPGA: remove transfer to HBM for the time being
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2023-09-11 20:24:20 +02:00 |
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309dabd32b
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FPGA: Use dedicated struct for address exchange
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2023-09-11 11:19:05 +02:00 |
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6cd8d768ea
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FPGA: save_to_hbm uses dedicated data structure for completion
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2023-09-11 10:50:15 +02:00 |
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48861aafcb
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FPGAAcquisitionDevice: Report HBM size
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2023-09-10 16:38:25 +02:00 |
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175aefc4b8
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FPGA: Save to HBM uses only 2 channels
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2023-09-10 09:54:32 +02:00 |
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929f6c6544
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FPGA: Handle HBM offsets internally in Jungfraujoch logic
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2023-09-09 20:50:41 +02:00 |
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aca1bbda0e
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HLSSimulatedDevice: moving towards continuous HBM representation
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2023-09-09 13:10:06 +02:00 |
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6251c58f32
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FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
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2023-09-08 19:08:37 +02:00 |
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c2eaee6d8a
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FPGA: Save to HBM operates in parallel to host writer
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2023-09-08 13:07:49 +02:00 |
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38df621cf6
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FPGA: Add save to HBM (work in progress)
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2023-09-07 22:15:20 +02:00 |
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347bfd3f2c
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HLSSimulateDevice: Remove reference to UltraRAM
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2023-09-07 21:39:14 +02:00 |
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3aeb3e09ee
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FPGA: Do not load internal packet generator frame via DMA
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2023-09-06 11:57:16 +02:00 |
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