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FPGA: save_to_hbm uses dedicated data structure for completion

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This commit is contained in:
leonarski_f
2023-09-11 10:50:15 +02:00
parent ae7ccfdcec
commit 6cd8d768ea
4 changed files with 33 additions and 38 deletions
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16
fpga/hls/hls_jfjoch.h
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@@ -70,6 +70,20 @@ struct axis_datamover_ctrl {
ap_uint<40+64> data;
};
struct axis_completion {
ap_uint<128> packet_mask;
ap_uint<64> frame_number;
ap_uint<64> exptime;
ap_uint<64> timestamp;
ap_uint<64> bunchid;
ap_uint<32> debug;
ap_uint<32> data_collection_id;
ap_uint<32> handle;
ap_uint<16> packet_count;
ap_uint<5> module;
ap_uint<1> flushing;
};
void setup_datamover (hls::stream<axis_datamover_ctrl> &datamover_cmd_stream, uint64_t address, size_t bytes_to_write);
void data_collection_fsm(AXI_STREAM &eth_in,
@@ -129,7 +143,7 @@ void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
void save_to_hbm(STREAM_512 &data_in,
hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_in,
hls::stream<ap_uint<32> > &completion_out,
hls::stream<axis_completion> &completion_out,
hls::burst_maxi<hbm256_t> d_hbm_p0, hls::burst_maxi<hbm256_t> d_hbm_p1,
volatile uint64_t &packets_processed,
volatile ap_uint<1> &idle,

2
fpga/hls/host_writer.cpp
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@@ -13,7 +13,7 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
const ap_uint<32> &handle,
const ap_uint<8> &module_number,
const ap_uint<64> &frame_num,
const ap_uint<256> &packet_mask,
const ap_uint<128> &packet_mask,
const ap_uint<16> &packet_count,
const ap_uint<32> &debug,
const ap_uint<64> &timestamp,

51
fpga/hls/save_to_hbm.cpp
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@@ -9,11 +9,11 @@
#define PACKET_SIZE 8192
inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
inline void write_completion(hls::stream<axis_completion> &m_axis_completion,
const ap_uint<32> &handle,
const ap_uint<8> &module_number,
const ap_uint<5> &module_number,
const ap_uint<64> &frame_num,
const ap_uint<256> &packet_mask,
const ap_uint<128> &packet_mask,
const ap_uint<16> &packet_count,
const ap_uint<32> &debug,
const ap_uint<64> &timestamp,
@@ -22,42 +22,23 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
const ap_uint<32> &data_collection_id,
const ap_uint<1> &flushing) {
#pragma HLS INLINE
ap_uint<1> all_packets_ok = packet_mask.and_reduce();
ap_uint<1> any_packets_received = packet_mask.or_reduce();
ap_uint<8> status = 0;
status[0] = all_packets_ok;
status[1] = any_packets_received;
status[2] = flushing;
ap_uint<128> tmp = (handle, packet_count, status, module_number, frame_num);
status[7] = tmp.xor_reduce(); // ensure completion has even parity
if (handle != HANDLE_SKIP_FRAME) {
m_axis_completion << handle;
m_axis_completion << (packet_count, status, module_number);
m_axis_completion << frame_num(63, 32);
m_axis_completion << frame_num(31, 0);
m_axis_completion << timestamp(63,32);
m_axis_completion << timestamp(31,0);
m_axis_completion << bunchid(63,32);
m_axis_completion << bunchid(31,0);
m_axis_completion << exptime;
m_axis_completion << debug;
m_axis_completion << 0;
m_axis_completion << data_collection_id;
m_axis_completion << packet_mask(127,96);
m_axis_completion << packet_mask( 95,64);
m_axis_completion << packet_mask( 63,32);
m_axis_completion << packet_mask( 31, 0);
}
axis_completion cmpl;
cmpl.handle = handle;
cmpl.module = module_number;
cmpl.frame_number = frame_num;
cmpl.packet_mask = packet_mask;
cmpl.packet_count = packet_count;
cmpl.debug = debug;
cmpl.timestamp = timestamp;
cmpl.bunchid = bunchid;
cmpl.exptime = exptime;
cmpl.data_collection_id = data_collection_id;
cmpl.flushing = flushing;
}
void save_to_hbm(STREAM_512 &data_in,
hls::stream<ap_uint<ADDR_STREAM_WIDTH> > &addr_in,
hls::stream<ap_uint<32> > &completion_out,
hls::stream<axis_completion> &completion_out,
hls::burst_maxi<hbm256_t> d_hbm_p0, hls::burst_maxi<hbm256_t> d_hbm_p1,
volatile uint64_t &packets_processed,
volatile ap_uint<1> &idle,

2
receiver/HLSSimulatedDevice.cpp
View File

@@ -319,7 +319,7 @@ void HLSSimulatedDevice::HLSMainThread() {
hls_cores.emplace_back([&] { writer_split(converted_2, converted_3, converted_4,
addr3, addr4, addr5); });
hls::stream<ap_uint<32> > save_to_hbm_completion;
hls::stream<axis_completion > save_to_hbm_completion;
ap_uint<8> save_to_hbm_err_reg;
uint64_t save_to_hbm_packets_processed;
ap_uint<1> save_to_hbm_idle;