HLSSimulateDevice: Remove reference to UltraRAM
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@@ -227,10 +227,7 @@ void HLSSimulatedDevice::HLSMainThread() {
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ap_uint<8> err_reg;
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std::vector<ap_uint<256>> d_uram_p0(MAX_MODULES_FPGA * RAW_MODULE_SIZE / 32);
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std::vector<ap_uint<256>> d_uram_p1(MAX_MODULES_FPGA * RAW_MODULE_SIZE / 32);
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while(!din_eth.empty())
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while(!din_eth.empty())
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ethernet(din_eth, ip1, arp1, mac_addr, eth_packets, clear_counters);
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while(!ip1.empty())
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@@ -299,12 +296,12 @@ void HLSSimulatedDevice::HLSMainThread() {
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// 2. Apply pedestal & gain corrections
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hls_cores.emplace_back([&] { jf_conversion(raw4, converted_1,
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addr2, addr3,
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d_uram_p0.data(), d_uram_p1.data(),
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(hbm256_t *) (hbm_memory[0].data()), (hbm256_t *) (hbm_memory[1].data()),
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(hbm256_t *) (hbm_memory[2].data()), (hbm256_t *) (hbm_memory[3].data()),
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(hbm256_t *) (hbm_memory[4].data()), (hbm256_t *) (hbm_memory[5].data()),
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(hbm256_t *) (hbm_memory[6].data()), (hbm256_t *) (hbm_memory[7].data()),
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(hbm256_t *) (hbm_memory[8].data()), (hbm256_t *) (hbm_memory[9].data())); });
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(hbm256_t *) (hbm_memory[8].data()), (hbm256_t *) (hbm_memory[9].data()),
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(hbm256_t *) (hbm_memory[10].data()), (hbm256_t *) (hbm_memory[11].data())); });
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// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
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hls_cores.emplace_back([&] { timer_host(converted_1, converted_2, counter_host); });
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@@ -21,7 +21,7 @@ class HLSSimulatedDevice : public FPGAAcquisitionDevice {
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ActionConfig cfg;
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volatile bool idle;
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std::vector<char> hbm_memory[10];
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std::vector<char> hbm_memory[16];
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hls::stream<ap_uint<32> > work_request_stream;
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hls::stream<ap_uint<32> > completion_stream;
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