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FPGA: Use HBM as intermediary cache for images

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This commit is contained in:
leonarski_f
2023-09-19 07:36:56 +02:00
parent 5b448c1b1a
commit 2982097b8c
7 changed files with 342 additions and 179 deletions
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fpga/hls/CMakeLists.txt
+11 -2
View File
@@ -13,7 +13,10 @@ ADD_LIBRARY( HLSSimulation STATIC
udp.cpp
sls_detector.cpp
frame_generator.cpp
stream_merge.cpp)
stream_merge.cpp
save_to_hbm.cpp
load_from_hbm.cpp
mask_missing.cpp)
TARGET_INCLUDE_DIRECTORIES(HLSSimulation PUBLIC ../include)
TARGET_LINK_LIBRARIES(HLSSimulation CommonFunctions)
@@ -46,6 +49,9 @@ MAKE_HLS_MODULE(udp.cpp udp)
MAKE_HLS_MODULE(sls_detector.cpp sls_detector)
MAKE_HLS_MODULE(frame_generator.cpp frame_generator)
MAKE_HLS_MODULE(stream_merge.cpp stream_merge)
MAKE_HLS_MODULE(load_from_hbm.cpp load_from_hbm)
MAKE_HLS_MODULE(save_to_hbm.cpp save_to_hbm)
MAKE_HLS_MODULE(mask_missing.cpp mask_missing)
SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip
psi_ch_hls_timer_host_1_0.zip
@@ -58,8 +64,11 @@ SET (HLS_IPS psi_ch_hls_data_collection_fsm_1_0.zip
psi_ch_hls_sls_detector_1_0.zip
psi_ch_hls_icmp_1_0.zip
psi_ch_hls_host_writer_1_0.zip
psi_ch_hls_load_from_hbm_1_0.zip
psi_ch_hls_save_to_hbm_1_0.zip
psi_ch_hls_mask_missing_1_0.zip
psi_ch_hls_frame_generator_1_0.zip
psi_ch_hls_stream_merge_1_0.zip)
psi_ch_hls_stream_merge_1_0.zip)
SET (HLS_IPS ${HLS_IPS} PARENT_SCOPE)
ADD_CUSTOM_TARGET(hls DEPENDS ${HLS_IPS})
fpga/hls/hls_jfjoch.h
+38 -2
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@@ -70,6 +70,19 @@ struct axis_addr {
ap_uint<1> last;
};
struct axis_completion {
ap_uint<128> packet_mask;
ap_uint<64> frame_number;
ap_uint<64> exptime;
ap_uint<64> timestamp;
ap_uint<64> bunchid;
ap_uint<32> debug;
ap_uint<16> handle;
ap_uint<8> packet_count;
ap_uint<7> module;
ap_uint<1> last;
};
void setup_datamover (hls::stream<axis_datamover_ctrl> &datamover_cmd_stream, uint64_t address, size_t bytes_to_write);
void data_collection_fsm(AXI_STREAM &eth_in,
@@ -118,14 +131,37 @@ void jf_conversion(STREAM_512 &data_in, STREAM_512 &data_out,
hls::burst_maxi<hbm256_t> d_hbm_p10, hls::burst_maxi<hbm256_t> d_hbm_p11);
void host_writer(STREAM_512 &data_in,
hls::stream<axis_addr> &addr_in,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<ap_axiu<512,1,1,1> > &host_memory_out,
hls::stream<axis_datamover_ctrl> &datamover_out_cmd,
hls::stream<ap_uint<32> > &s_axis_work_request,
hls::stream<ap_uint<32> > &m_axis_completion,
volatile uint64_t &packets_processed,
volatile ap_uint<1> &idle,
ap_uint<8> &err_reg);
volatile ap_uint<8> &err_reg);
void load_from_hbm(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16> > &m_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<32> hbm_size_bytes);
void save_to_hbm(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<axis_addr> &addr_in,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16>> &s_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<32> hbm_size_bytes) ;
void mask_missing(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion);
void timer_host(STREAM_512 &data_in,
STREAM_512 &data_out,
fpga/hls/host_writer.cpp
+44 -170
View File
@@ -19,15 +19,13 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
const ap_uint<64> &timestamp,
const ap_uint<64> &bunchid,
const ap_uint<32> &exptime,
const ap_uint<32> &data_collection_id,
const ap_uint<1> &flushing) {
const ap_uint<16> &data_collection_id) {
#pragma HLS INLINE
ap_uint<1> all_packets_ok = packet_mask.and_reduce();
ap_uint<1> any_packets_received = packet_mask.or_reduce();
ap_uint<8> status = 0;
status[0] = all_packets_ok;
status[1] = any_packets_received;
status[2] = flushing;
ap_uint<128> tmp = (handle, packet_count, status, module_number, frame_num);
status[7] = tmp.xor_reduce(); // ensure completion has even parity
@@ -56,8 +54,8 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
inline ap_uint<1> read_request(hls::stream<ap_uint<32> > &s_axis_work_request,
ap_uint<32> &handle,
ap_uint<64> &address) {
ap_uint<32> &handle,
ap_uint<64> &address) {
#pragma HLS INLINE
ap_uint<32> tmp1, tmp2, tmp3, tmp4;
@@ -78,200 +76,76 @@ inline ap_uint<1> read_request(hls::stream<ap_uint<32> > &s_axis_work_request,
}
void host_writer(STREAM_512 &data_in,
hls::stream<axis_addr> &addr_in,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<ap_axiu<512,1,1,1> > &host_memory_out,
hls::stream<axis_datamover_ctrl> &datamover_out_cmd,
hls::stream<ap_uint<32> > &s_axis_work_request,
hls::stream<ap_uint<32> > &m_axis_completion,
volatile uint64_t &packets_processed,
volatile ap_uint<1> &idle,
ap_uint<8> &err_reg) {
volatile ap_uint<8> &err_reg) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=s_axis_completion
#pragma HLS INTERFACE register both axis port=host_memory_out
#pragma HLS INTERFACE register both axis port=addr_in
#pragma HLS INTERFACE register both axis port=datamover_out_cmd
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_work_request
#pragma HLS INTERFACE register ap_none port=idle
#pragma HLS INTERFACE register ap_vld port=packets_processed
#pragma HLS INTERFACE register ap_vld port=err_reg
#pragma HLS INTERFACE register ap_none port=idle
ap_uint<128> packet_mask[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=packet_mask core=RAM_1P
ap_uint<16> packet_count[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=packet_count core=RAM_1P
ap_uint<32> handle[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=handle core=RAM_1P
ap_uint<64> curr_frame[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=curr_frame core=RAM_1P
ap_uint<32> debug[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=debug core=RAM_1P
ap_uint<64> timestamp[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=timestamp core=RAM_1P
ap_uint<32> exptime[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=exptime core=RAM_1P
ap_uint<64> jf_bunchid[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=jf_bunchid core=RAM_1P
ap_uint<64> curr_offset[MAX_MODULES_FPGA*2];
#pragma HLS RESOURCE variable=curr_offset core=RAM_1P
idle = 1;
for (int i = 0; i < MAX_MODULES_FPGA*2; i++) {
#pragma HLS UNROLL
curr_frame[i] = UINT64_MAX;
handle[i] = 0;
packet_mask[i] = 0;
packet_count[i] = 0;
curr_offset[i] = 0;
debug[i] = 0;
timestamp[i] = 0;
exptime[i] = 0;
jf_bunchid[i] = 0;
}
ap_uint<32> req_handle;
ap_uint<64> req_host_offset;
while (data_in.empty()) {
#pragma HLS PIPELINE II=4
if (!s_axis_work_request.empty())
read_request(s_axis_work_request, req_handle, req_host_offset);
}
axis_addr addr;
addr_in >> addr;
packet_512_t packet_in;
data_in >> packet_in;
ap_uint<5> nmodules = ACT_REG_NMODULES(packet_in.data);
ap_uint<32> data_collection_mode = ACT_REG_MODE(packet_in.data);
ap_uint<32> data_collection_id = data_collection_mode(31, 16); // upper 16-bit of mode
packet_512_t packet;
data_in >> packet;
ap_uint<32> data_collection_mode = ACT_REG_MODE(packet.data);
ap_uint<16> data_collection_id = data_collection_mode(31, 16);
ap_uint<1> mode_nonblocking = (data_collection_mode & MODE_NONBLOCKING_ON_WR) ? 1 : 0;
ap_uint<8> internal_err_reg = 0;
err_reg = internal_err_reg;
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0);
err_reg = 0;
idle = 0;
uint64_t total_counter = 0;
packets_processed = 0;
addr_in >> addr;
uint64_t internal_packets_processed = 0;
packets_processed = internal_packets_processed;
ap_axiu<512,1,1,1> packet_out;
packet_out.keep = UINT64_MAX;
packet_out.strb = UINT64_MAX;
packet_out.dest = 0;
packet_out.id = 0;
packet_out.user = 0;
Loop_good_packet:
while (!addr.last) {
// Process one UDP packet per iteration
#pragma HLS PIPELINE II=128
ap_uint<64> frame_number = addr.frame_number;
ap_uint<4> module_number = addr.module;
ap_uint<7> eth_packet = addr.eth_packet;
ap_uint<5> id = module_number * 2 + (frame_number % 2);
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id);
if (curr_frame[id] != frame_number) {
if (packet_mask[id] != 0) {
ap_uint<32> comp_handle = handle[id];
ap_uint<64> comp_frame = curr_frame[id];
ap_uint<256> comp_packet_mask = packet_mask[id];
ap_uint<16> comp_packet_count = packet_count[id];
ap_uint<32> comp_debug = debug[id];
ap_uint<64> comp_timestamp = timestamp[id];
ap_uint<64> comp_bunchid = jf_bunchid[id];
ap_uint<32> comp_exptime = exptime[id];
write_completion(m_axis_completion, comp_handle, module_number,
comp_frame, comp_packet_mask, comp_packet_count,
comp_debug, comp_timestamp, comp_bunchid,
comp_exptime, data_collection_id, 0);
}
if (module_number >= nmodules) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[5] = 1;
} else if (s_axis_work_request.empty() && mode_nonblocking) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
} else {
if (read_request(s_axis_work_request, req_handle, req_host_offset))
internal_err_reg[2] = 1;
if (req_handle >= HANDLE_SKIP_FRAME) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[4] = 1;
}
}
handle[id] = req_handle;
curr_frame[id] = frame_number;
curr_offset[id] = req_host_offset;
debug[id] = addr.debug;
timestamp[id] = addr.timestamp;
jf_bunchid[id] = addr.bunchid;
exptime[id] = addr.exptime;
packet_mask[id] = ap_uint<128>(1) << eth_packet;
packet_count[id] = 1;
axis_completion cmpl;
s_axis_completion >> cmpl;
while (!cmpl.last) {
if (s_axis_work_request.empty() && mode_nonblocking) {
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++)
data_in >> packet;
} else {
packet_count[id]++;
packet_mask[id] |= ap_uint<128>(1) << eth_packet;
}
ap_uint<32> req_handle;
ap_uint<64> req_host_offset;
if (handle[id] != HANDLE_SKIP_FRAME) {
for (int i = 0; i < 128; i++) {
data_in >> packet_in;
packet_out.data = packet_in.data;
packet_out.last = packet_in.last;
host_memory_out << packet_out;
read_request(s_axis_work_request, req_handle, req_host_offset);
setup_datamover(datamover_out_cmd, req_host_offset, RAW_MODULE_SIZE * sizeof(uint16_t));
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
data_in >> packet;
host_memory_out << packet;
}
if (packet_in.last != 1)
internal_err_reg[1] = 1;
size_t out_frame_addr = curr_offset[id] + eth_packet * PACKET_SIZE;
if (out_frame_addr % 128 != 0) internal_err_reg[0] = 1;
if (curr_offset[id] == 0) internal_err_reg[3] = 1;
total_counter++;
packets_processed = total_counter;
setup_datamover(datamover_out_cmd, out_frame_addr, PACKET_SIZE);
} else {
for (int i = 0; i < 128; i++)
data_in >> packet_in;
if (packet_in.last != 1)
internal_err_reg[1] = 1;
write_completion(m_axis_completion,
req_handle,
cmpl.module,
cmpl.frame_number,
cmpl.packet_mask,
cmpl.packet_count,
cmpl.debug,
cmpl.timestamp,
cmpl.bunchid,
cmpl.exptime,
data_collection_id);
internal_packets_processed += cmpl.packet_count;
packets_processed = internal_packets_processed;
}
addr_in >> addr;
err_reg = internal_err_reg;
s_axis_completion >> cmpl;
}
#ifndef __SYNTHESIS__
while (!host_memory_out.empty())
std::this_thread::sleep_for(std::chrono::milliseconds(100));
#endif
data_in >> packet;
for (ap_uint<8> m = 0; m < nmodules * 2; m++) {
#pragma HLS PIPELINE II=16
if (packet_mask[m] != 0)
write_completion(m_axis_completion, handle[m], m / 2, curr_frame[m],
packet_mask[m], packet_count[m],
debug[m], timestamp[m], jf_bunchid[m],
exptime[m], data_collection_id, 1);
}
data_in >> packet_in;
write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0);
idle = 1;
write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id);
}
fpga/hls/load_from_hbm.cpp
+66
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@@ -0,0 +1,66 @@
// Copyright (2019-2023) Paul Scherrer Institute
// SPDX-License-Identifier: GPL-3.0-or-later
#include "hls_jfjoch.h"
void load_from_hbm(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16> > &m_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<32> hbm_size_bytes) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=data_out
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_completion
#pragma HLS INTERFACE register both axis port=m_axis_free_handles
#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
max_read_burst_length=16 max_write_burst_length=2 latency=120 num_write_outstanding=2 num_read_outstanding=8
ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32;
ap_uint<32> offset_hbm_1 = 14 * hbm_size_bytes / 32;
packet_512_t packet;
data_in >> packet;
data_out << packet;
for (ap_uint<16> i = 0; i < hbm_size_bytes / (RAW_MODULE_SIZE * sizeof(uint32_t) / 2); i++)
m_axis_free_handles << i;
axis_completion cmpl;
s_axis_completion >> cmpl;
while (!cmpl.last) {
m_axis_completion << cmpl;
size_t offset = (cmpl.handle * RAW_MODULE_SIZE * sizeof(uint16_t)) / 64;
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
packet_512_t packet_out;
packet_out.data(255, 0) = d_hbm_p0[offset_hbm_0 + offset + i];
packet_out.data(511, 256) = d_hbm_p1[offset_hbm_1 + offset + i];
packet_out.last = (i == RAW_MODULE_SIZE * sizeof(uint16_t) / 64 - 1);
packet_out.id = 0;
packet_out.dest = 0;
packet_out.keep = UINT64_MAX;
packet_out.strb = UINT64_MAX;
packet_out.user = 0;
data_out << packet_out;
}
m_axis_free_handles << cmpl.handle;
s_axis_completion >> cmpl;
}
m_axis_completion << cmpl;
m_axis_free_handles << UINT16_MAX;
data_in >> packet;
data_out << packet;
}
fpga/hls/mask_missing.cpp
+39
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@@ -0,0 +1,39 @@
// Copyright (2019-2023) Paul Scherrer Institute
// SPDX-License-Identifier: GPL-3.0-or-later
#include "hls_jfjoch.h"
void mask_missing(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<axis_completion > &s_axis_completion,
hls::stream<axis_completion > &m_axis_completion) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=data_out
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_completion
packet_512_t packet;
data_in >> packet;
data_out << packet;
axis_completion cmpl;
s_axis_completion >> cmpl;
while (!cmpl.last) {
m_axis_completion << cmpl;
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {
#pragma HLS PIPELINE II=1
data_in >> packet;
if (!cmpl.packet_mask[i / 128]) {
for (int j = 0; j < 512; j++)
packet.data[j] = 1;
}
data_out << packet;
}
s_axis_completion >> cmpl;
}
m_axis_completion << cmpl;
data_in >> packet;
data_out << packet;
}
fpga/hls/save_to_hbm.cpp
+105
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@@ -0,0 +1,105 @@
// Copyright (2019-2023) Paul Scherrer Institute
// SPDX-License-Identifier: GPL-3.0-or-later
#include "hls_jfjoch.h"
void save_to_hbm(STREAM_512 &data_in,
STREAM_512 &data_out,
hls::stream<axis_addr> &addr_in,
hls::stream<axis_completion > &m_axis_completion,
hls::stream<ap_uint<16>> &s_axis_free_handles,
ap_uint<256> *d_hbm_p0,
ap_uint<256> *d_hbm_p1,
ap_uint<32> hbm_size_bytes) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE register both axis port=data_in
#pragma HLS INTERFACE register both axis port=data_out
#pragma HLS INTERFACE register both axis port=addr_in
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_free_handles
#pragma HLS INTERFACE mode=ap_none port=hbm_size_bytes
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p0 bundle=d_hbm_p0 depth=512 offset=off \
max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
#pragma HLS INTERFACE mode=m_axi port=d_hbm_p1 bundle=d_hbm_p1 depth=512 offset=off \
max_read_burst_length=2 max_write_burst_length=16 latency=120 num_write_outstanding=8 num_read_outstanding=2
ap_uint<32> offset_hbm_0 = 12 * hbm_size_bytes / 32;
ap_uint<32> offset_hbm_1 = 14 * hbm_size_bytes / 32;
axis_completion cmpl[MAX_MODULES_FPGA*2];
for (int i = 0; i < MAX_MODULES_FPGA*2; i++) {
#pragma HLS UNROLL
cmpl[i].frame_number = UINT64_MAX;
cmpl[i].packet_mask = 0;
cmpl[i].last = 0;
}
axis_addr addr;
addr_in >> addr;
packet_512_t packet_in;
data_in >> packet_in;
data_out << packet_in;
addr_in >> addr;
Loop_good_packet:
while (!addr.last) {
// Process one UDP packet per iteration
#pragma HLS PIPELINE II=128
ap_uint<64> frame_number = addr.frame_number;
ap_uint<5> module_number = addr.module;
ap_uint<7> eth_packet = addr.eth_packet;
ap_uint<5> id = module_number * 2 + (frame_number % 2);
ap_uint<16> curr_handle = 0;
if (cmpl[id].frame_number != frame_number) {
if (cmpl[id].packet_mask != 0)
m_axis_completion << cmpl[id];
cmpl[id].module = addr.module;
cmpl[id].frame_number = addr.frame_number;
cmpl[id].timestamp = addr.timestamp;
cmpl[id].exptime = addr.exptime;
cmpl[id].debug = addr.debug;
cmpl[id].bunchid = addr.bunchid;
cmpl[id].last = 0;
cmpl[id].packet_mask = ap_uint<128>(1) << eth_packet;
cmpl[id].packet_count = 1;
curr_handle = s_axis_free_handles.read();
cmpl[id].handle = curr_handle;
} else {
cmpl[id].packet_mask |= ap_uint<128>(1) << eth_packet;
cmpl[id].packet_count++;
}
size_t offset = (cmpl[id].handle * RAW_MODULE_SIZE * sizeof(uint16_t) + eth_packet * 8192) / 64;
for (int i = 0; i < 128; i++) {
data_in >> packet_in;
d_hbm_p0[offset_hbm_0 + offset + i] = packet_in.data(255, 0);
d_hbm_p1[offset_hbm_1 + offset + i] = packet_in.data(511, 256);
}
addr_in >> addr;
}
for (ap_uint<8> m = 0; m < MAX_MODULES_FPGA * 2; m++) {
#pragma HLS PIPELINE II=16
if (cmpl[m].packet_mask != 0)
m_axis_completion << cmpl[m];
}
data_in >> packet_in;
data_out << packet_in;
m_axis_completion << axis_completion{.last = 1};
ap_uint<16> tmp = s_axis_free_handles.read();
while (tmp != UINT16_MAX)
tmp = s_axis_free_handles.read();
}
receiver/HLSSimulatedDevice.cpp
+39 -5
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@@ -214,8 +214,11 @@ void HLSSimulatedDevice::HLSMainThread() {
STREAM_512 raw2;
STREAM_512 raw3;
STREAM_512 converted_0;
STREAM_512 converted_1;
STREAM_512 converted_2;
STREAM_512 converted_3;
STREAM_512 converted_4;
hls::stream<axis_addr> addr0;
hls::stream<axis_addr> addr1;
@@ -289,7 +292,7 @@ void HLSSimulatedDevice::HLSMainThread() {
hls_cores.emplace_back([&] { timer_host(raw1, raw2, counter_hbm); });
// 2. Apply pedestal & gain corrections
hls_cores.emplace_back([&] { jf_conversion(raw2, converted_1,
hls_cores.emplace_back([&] { jf_conversion(raw2, converted_0,
addr1, addr2,
hbm.data(),
hbm.data(),
@@ -304,12 +307,22 @@ void HLSSimulatedDevice::HLSMainThread() {
hbm.data(),
hbm.data()); });
// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { timer_host(converted_1, converted_2, counter_host); });
hls::stream<axis_completion> compl0, compl1, compl2;
hls::stream<ap_uint<16>> handles;
// 3. Prepare data to write to host memory
// 3. Cache images in HBM
hls_cores.emplace_back([&] { save_to_hbm(converted_0, converted_1, addr2, compl0, handles, hbm.data(), hbm.data(), hbm_if_size);});
hls_cores.emplace_back([&] { load_from_hbm(converted_1, converted_2, compl0, compl1, handles, hbm.data(), hbm.data(), hbm_if_size);});
// 4. Mask missing pixels
hls_cores.emplace_back([&] { mask_missing(converted_2, converted_3, compl1, compl2);});
// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { timer_host(converted_3, converted_4, counter_host); });
// 5. Prepare data to write to host memory
hls_cores.emplace_back([&] {
host_writer(converted_2, addr2, datamover_out.GetDataStream(),
host_writer(converted_4, compl2, datamover_out.GetDataStream(),
datamover_out.GetCtrlStream(), work_request_stream, completion_stream,
packets_processed, host_writer_idle, err_reg); });
@@ -337,12 +350,33 @@ void HLSSimulatedDevice::HLSMainThread() {
if (!raw3.empty())
throw std::runtime_error("Raw3 queue not empty");
if (!converted_0.empty())
throw std::runtime_error("Converted_0 queue not empty");
if (!converted_1.empty())
throw std::runtime_error("Converted_1 queue not empty");
if (!converted_2.empty())
throw std::runtime_error("Converted_2 queue not empty");
if (!converted_3.empty())
throw std::runtime_error("Converted_3 queue not empty");
if (!converted_4.empty())
throw std::runtime_error("Converted_4 queue not empty");
if (!compl0.empty())
throw std::runtime_error("Compl0 queue not empty");
if (!compl1.empty())
throw std::runtime_error("Compl1 queue not empty");
if (!compl2.empty())
throw std::runtime_error("Compl2 queue not empty");
if (!handles.empty())
throw std::runtime_error("Handles queue not empty");
if (!datamover_in.GetDataStream().empty())
throw std::runtime_error("Datamover queue is not empty");