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a94bdacea9
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Revert "FPGA: use 4 HBM interfaces for load and save to HBM"
This reverts commit 28a29ea3183a35d8ba0dda0628ac727f8bfe4f17.
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2023-09-19 07:36:56 +02:00 |
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1fe5c474ee
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FPGA: use 4 HBM interfaces for load and save to HBM
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2023-09-19 07:36:56 +02:00 |
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e041e7bf26
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Revert "FPGA: double HBM latency & number of outstanding operations"
This reverts commit 0f903607a028e1827dd965b13f87f913cc81d6b1.
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2023-09-19 07:36:56 +02:00 |
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480eb5527b
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FPGA: double HBM latency & number of outstanding operations
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2023-09-19 07:36:56 +02:00 |
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357e2c01f6
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FPGA: hbm_size_bytes is constant in action_config.v
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2023-09-19 07:36:56 +02:00 |
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6700fe54f8
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FPGA: hbm_size_bytes in load_from_hbm and save_to_hbm is read after first data package is exchanged
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2023-09-19 07:36:56 +02:00 |
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5f5b59ef30
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FPGA: Increase FIFO just before save_to_hbm
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2023-09-19 07:36:56 +02:00 |
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95d4844aa4
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FPGA: Use both HBM pseudo-channels
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2023-09-19 07:36:56 +02:00 |
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e194d31ee1
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FPGA: Add register slices
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2023-09-19 07:36:56 +02:00 |
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36cd247377
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FPGA: Integrate HBM cache into the FPGA
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2023-09-19 07:36:56 +02:00 |
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2982097b8c
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FPGA: Use HBM as intermediary cache for images
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2023-09-19 07:36:56 +02:00 |
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5b448c1b1a
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GPUImageAnalysis: Fix to allow compilation without CUDA
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2023-09-19 07:36:20 +02:00 |
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4375d992ff
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CMake: Use static HDF5 library
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2023-09-19 07:28:40 +02:00 |
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121aef36ba
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recv.json: Update host address
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2023-09-16 13:19:51 +02:00 |
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e0fd52b31b
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jjofhc_grpc2http.py use relative directory
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2023-09-16 12:57:01 +02:00 |
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a67da96bee
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broker.json: Adapt to 9M
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2023-09-16 12:56:41 +02:00 |
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ca55ade211
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Merge branch 'fpga_easy_recover' into 'main'
Recent updates
See merge request jungfraujoch/nextgendcu!6
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2023-09-15 12:35:36 +02:00 |
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90cd9602e2
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Update slsDetectorPackage to 7.0.2
Signed-off-by: Filip Leonarski <filip.leonarski@psi.ch>
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2023-09-15 12:21:31 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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46c1cebab5
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Merge branch 'fpga_frame_generator' into 'fpga_easy_recover'
FPGA: Replace internal_packet_generator with frame_generator
See merge request jungfraujoch/nextgendcu!5
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2023-09-15 09:53:34 +02:00 |
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362eb62d4b
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FPGA: Use own function to merge streams instead of AXI-Switch + more FIFO status saved
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2023-09-14 23:58:17 +02:00 |
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7a026b89d0
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FPGAIntegrationTest: Use blocking mode for one remaining test
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2023-09-14 23:48:02 +02:00 |
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0a152f7b5a
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PCIe driver: check Ethernet aligned twice
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2023-09-14 23:43:01 +02:00 |
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aee9d0e6fc
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jfjoch_action_test: Set IPv4 and MAC addresses
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2023-09-14 17:54:33 +02:00 |
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ab1a8fbfca
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PCIExpressDevice: Get MAC/IPv4 Address for internal packet generator via ioctl
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2023-09-14 17:48:30 +02:00 |
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48ee2ca305
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FPGAAcquisitionDevice: Fix reporting of FIFO status
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2023-09-14 16:31:24 +02:00 |
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886a84ee9f
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PCIExpressDevice: Wrong function parameter
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2023-09-14 16:16:30 +02:00 |
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5d8a85071e
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PCIe driver: Fix missing return value in a function
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2023-09-14 15:56:52 +02:00 |
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aa263a329e
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Make test more repeatable by removing non-blocking mode in HLS simulation
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2023-09-13 21:51:40 +02:00 |
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0b95456d3d
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Adapt PCIe driver and tests for the new frame generator
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2023-09-13 21:44:20 +02:00 |
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f3e85deb31
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FPGA: Increase PCIe BAR size to 16 MB
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2023-09-13 20:55:10 +02:00 |
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0c471b3760
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FPGA: Some clean-up of frame generator
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2023-09-13 20:53:55 +02:00 |
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496d016c31
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FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets)
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2023-09-13 20:06:09 +02:00 |
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95d20085dd
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FPGA: Use volatile variable for counter
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2023-09-13 10:35:02 +02:00 |
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33a15e87df
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PCIe driver: minor fixes
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2023-09-13 08:00:55 +02:00 |
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0b4320c381
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PCIe driver: enable DMA
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2023-09-13 07:58:20 +02:00 |
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56993d3597
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FPGA: minor clean-up of network routines
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2023-09-12 21:35:37 +02:00 |
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b7239331ac
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FPGA: remove script from OC-Accel
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2023-09-12 21:10:15 +02:00 |
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5e137a514a
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FPGA: add more FIFOs to monitoring
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2023-09-12 20:35:48 +02:00 |
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8626195091
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FPGA: fix to deadlock
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2023-09-12 20:09:11 +02:00 |
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9d01630cfc
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FPGA: load calibration works as dedicated function of the card
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2023-09-12 14:34:42 +02:00 |
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7a635f1ee8
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FPGA: load_calibration clean-up + simplification
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2023-09-12 09:16:45 +02:00 |
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2b29381f87
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FPGA: update in timer code
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2023-09-12 08:16:44 +02:00 |
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8c3a25a8ad
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FPGA: load calibration operates directly on HBM
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2023-09-11 21:47:29 +02:00 |
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f98b5fe389
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FPGA: use only two HBM channels to write calibration in JF conversion
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2023-09-11 20:30:46 +02:00 |
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05000bab1f
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FPGA: remove transfer to HBM for the time being
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2023-09-11 20:24:20 +02:00 |
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0c524f9a3c
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FPGA: Add module to load images from HBM
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2023-09-11 12:42:38 +02:00 |
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253b409d38
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FPGA: Mark last completion saved to HBM
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2023-09-11 12:20:07 +02:00 |
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309dabd32b
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FPGA: Use dedicated struct for address exchange
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2023-09-11 11:19:05 +02:00 |
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9ff8e039d7
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FPGA: use HBM channels 12 and 13 for save_to_hbm
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2023-09-11 10:50:30 +02:00 |
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