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PCIe driver: minor fixes

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This commit is contained in:
leonarski_f
2023-09-13 08:00:55 +02:00
parent 0b4320c381
commit 33a15e87df
2 changed files with 6 additions and 10 deletions
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fpga/pcie_driver/jfjoch_drv.h
+2
View File
@@ -48,6 +48,8 @@
#define ADDR_LOAD_CALIBRATION_SC (0x000018)
#define ADDR_LOAD_CALIBRATION_MEM (0x002000)
#define JFJOCH_DMA_SETTINGS (XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR \
| XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED | XDMA_CTRL_STM_MODE_WB)
#define ADDR_CMS_CONTROL_REG 0x028018
#define ADDR_CMS_MB_RESETN_REG 0x020000
fpga/pcie_driver/jfjoch_function.c
+4 -10
View File
@@ -14,17 +14,13 @@ DEFINE_MUTEX(send_wr_mutex);
DEFINE_MUTEX(read_wc_mutex);
void jfjoch_start(struct jfjoch_drvdata *drvdata) {
u32 run_val = XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR
| XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED
| XDMA_CTRL_STM_MODE_WB; // Disable stream writeback
// Set PCIe beats counters
iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
// Start DMA
// RUN ==> C2H channel 0 control register
iowrite32(run_val, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
// Run C2H
iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
// Set Mailbox FIFOs, so interrupt threshold is 16 messages
// => This way it ensures that one can always execute read/write operation on the FIFO
@@ -306,12 +302,10 @@ int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig
}
// Start DMA
// RUN + enable logging of certain error conditions ==> H2C channel 0 control register
u32 run_val = XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR
| XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED | XDMA_CTRL_STM_MODE_WB;
// Clear counters and RUN H2C
iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
iowrite32(run_val, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
iowrite32(config->nmodules, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_MOD);
iowrite32(config->nstorage_cells, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_SC);