diff --git a/fpga/pcie_driver/jfjoch_drv.h b/fpga/pcie_driver/jfjoch_drv.h
index fed30437..e5d29cd0 100644
--- a/fpga/pcie_driver/jfjoch_drv.h
+++ b/fpga/pcie_driver/jfjoch_drv.h
@@ -48,6 +48,8 @@
 #define ADDR_LOAD_CALIBRATION_SC      (0x000018)
 #define ADDR_LOAD_CALIBRATION_MEM     (0x002000)
 
+#define JFJOCH_DMA_SETTINGS (XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR \
+                             | XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED | XDMA_CTRL_STM_MODE_WB)
 
 #define ADDR_CMS_CONTROL_REG          0x028018
 #define ADDR_CMS_MB_RESETN_REG        0x020000
diff --git a/fpga/pcie_driver/jfjoch_function.c b/fpga/pcie_driver/jfjoch_function.c
index 1c516252..f5f8e451 100644
--- a/fpga/pcie_driver/jfjoch_function.c
+++ b/fpga/pcie_driver/jfjoch_function.c
@@ -14,17 +14,13 @@ DEFINE_MUTEX(send_wr_mutex);
 DEFINE_MUTEX(read_wc_mutex);
 
 void jfjoch_start(struct jfjoch_drvdata *drvdata) {
-    u32 run_val = XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR
-                  | XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED
-                  | XDMA_CTRL_STM_MODE_WB; // Disable stream writeback
-
     // Set PCIe beats counters
     iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
     iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0xC0);
 
     // Start DMA
-    // RUN ==> C2H channel 0 control register
-    iowrite32(run_val, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
+    // Run C2H
+    iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (1<<12) + 0x04);
 
     // Set Mailbox FIFOs, so interrupt threshold is 16 messages
     // => This way it ensures that one can always execute read/write operation on the FIFO
@@ -306,12 +302,10 @@ int jfjoch_load_calibration(struct jfjoch_drvdata *drvdata, struct ActionConfig
     }
 
     // Start DMA
-    // RUN + enable logging of certain error conditions ==> H2C channel 0 control register
-    u32 run_val = XDMA_CTRL_RUN_STOP | XDMA_CTRL_IE_DESC_ALIGN_MISMATCH | XDMA_CTRL_IE_DESC_ERROR | XDMA_CTRL_IE_READ_ERROR
-                  | XDMA_CTRL_IE_WRITE_ERROR | XDMA_CTRL_IE_DESC_COMPLETED | XDMA_CTRL_STM_MODE_WB;
+    // Clear counters and RUN H2C
     iowrite32((1 << 1), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
     iowrite32((1 << 2), drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0xC0);
-    iowrite32(run_val, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
+    iowrite32(JFJOCH_DMA_SETTINGS, drvdata->bar0 + PCIE_OFFSET + (0<<12) + 0x04);
 
     iowrite32(config->nmodules, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_MOD);
     iowrite32(config->nstorage_cells, drvdata->bar0 + LOAD_CALIBRATION_OFFSET + ADDR_LOAD_CALIBRATION_SC);