FPGA: Use volatile variable for counter

fpga/hls/hls_jfjoch.h

@@ -115,7 +115,9 @@ void host_writer(STREAM_512 &data_in,
                  volatile ap_uint<1> &idle,
                  ap_uint<8> &err_reg);
 
-void timer_host(STREAM_512 &data_in, STREAM_512 &data_out, uint64_t &counter);
+void timer_host(STREAM_512 &data_in,
+                STREAM_512 &data_out,
+                volatile uint64_t &counter);
 
 void internal_packet_generator(STREAM_512 &data_in, STREAM_512 &data_out,
                                hls::stream<axis_addr> &addr_in,

fpga/hls/timer.cpp

@@ -3,7 +3,7 @@
 
 #include "hls_jfjoch.h"
 
-void timer_host(STREAM_512 &data_in, STREAM_512 &data_out, uint64_t &counter) {
+void timer_host(STREAM_512 &data_in, STREAM_512 &data_out, volatile uint64_t &counter) {
 #pragma HLS INTERFACE register both axis port=data_in
 #pragma HLS INTERFACE register both axis port=data_out
 #pragma HLS INTERFACE register ap_vld port=counter