FPGA: update in timer code

fpga/hls/timer.cpp

@@ -16,17 +16,16 @@ void timer_host(STREAM_512 &data_in, STREAM_512 &data_out, uint64_t &counter) {
     data_out << packet_in;
 
     data_in >> packet_in;
-
     while (!packet_in.user) {
-#pragma HLS PIPELINE
+#pragma HLS PIPELINE II=1
         if (data_out.full()) {
             if (counter_internal < UINT64_MAX)
                 counter_internal++;
-            counter = counter_internal;
         } else {
             data_out << packet_in;
             data_in >> packet_in;
         }
+        counter = counter_internal;
     }
     data_out << packet_in;
 }