This patch addresses issues I occasionally observed:
a) I have seen occurrences when the GTX deasserts RXBYTEISALIGNED
while the RXLOSSOFSYNC is *not* asserted.
The comma-alignment state machine can be stuck in 'idle' believing
all is well when in fact RXBYTEISALIGNED is deasserted.
The proposed patch monitors RXBYTEISALIGNED in addition to
RXLOSSOFSYNC in 'idle' state.
b) The synchronizer (inst_cdc_fast_stat) which takes the pulse
width/delay to the EVR clock domain relies on a proper
reset sequence for correct operation.
It is possible, however, that the 'evr_clk' (which is generated
from the recovered RX clock) is not ticking at all when 'xuser_RESET'
resets said synchronizer. If e.g., there is no GTX reference clock
present (because it requires i2c initialization which is performed
later) then the EVR clock may not be ticking and prevent the
destination side of the synchronizer from being reset. This
has the consequence of 'width' and 'delay' *never* being
updated.
The proposed patch asserts the synchronizer reset while the RX PLL
and/or MMCM are not locked.
