Extend with Event Recorder Functionality

Changelog.md

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+## 2.1
+
+* Added Features
+  * Event Recorder functionality implemented as an option
+  * IFC1210 bindings for tosca2
+* Bugfixes
+  * None
+
+## 2.0
+
+* Migration from CVS /G/GPAC/Lib/Vivado_Lib/axi_evr320_2.0

README.md

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+## General Information
+
+The EVR320 Embedded Event Receiver (EEVR) is able to connect with a MRF Timing System. 
+Mainly the EEVR is used to decode configurable events and use them in firmware as triggers. 
+
+## Maintainer
+
+Patric Bucher [patric.bucher@psi.ch]
+
+## Authors
+
+Waldemar Koprek [waldemar.koprek@psi.ch]
+
+Goran Marinkovic [goran.marinkovic@psi.ch]
+
+Patric Bucher [patric.bucher@psi.ch]
+
+## Documentation
+
+See [EVR320 Documentation](doc/evr320.pdf "doc/evr320.pdf")
+
+## Changelog
+
+See [Changelog](Changelog.md)
+
+## What belongs into this Library
+
+All components and wrappers to connect various buses (AXI4, TOSCA-II, ..) and to use on different Xilinx FPGA's.
+
+Examples for things that belong into this library:
+* Event Decoder / Core Functionality
+* Different MGT types
+
+Examples for things that do not belong into this library:
+* Vivado IP Packager related files -> belong to separate git repo
+
+## Dependencies
+### Library
+* Libraries/TCL/PsiSim
+* Libraries/BoardSupport/ifc1210/tosca2 (with tosca2 only)
+
+
+

hdl/evr320_buffer.vhd

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+--------------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+--------------------------------------------------------------------------------
+-- Unit    : evr320_buffer.vhd
+-- Author  : Waldemar Koprek, Section Diagnostic
+--           Goran Marinkovic, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Copyright<68> PSI, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Comment :
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.math_real.all;
+
+
+entity evr320_buffer is
+   generic 
+   (
+      MEM_SIZE_BYTE              : integer := 2048;
+      MEM_DOB_WIDTH              : integer := 32
+   );
+   port
+   (
+      -- port a
+      clka                        : in    std_logic;
+      ena                         : in    std_logic;
+      wea                         : in    std_logic;
+      addra                       : in    std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE))))-1 downto  0);
+      dia                         : in    std_logic_vector( 7 downto  0);
+      page                        : in    std_logic;
+      -- port b
+      clkb                        : in    std_logic;
+      enb                         : in    std_logic;
+      addrb                       : in    std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE/(MEM_DOB_WIDTH/8)))))-1 downto  0);
+      dob                         : out   std_logic_vector(MEM_DOB_WIDTH-1 downto  0)
+   );
+   
+   attribute ram_style                         : string;
+   attribute ram_style of evr320_buffer        : entity is "block";
+
+end evr320_buffer;
+
+architecture behavioral of evr320_buffer is
+
+   type ram_type_d32 is array ((2*MEM_SIZE_BYTE)-1 downto 0) of std_logic_vector( 7 downto  0);
+   shared variable RAM            : ram_type_d32;
+      
+   type ram_type_d64 is array (MEM_SIZE_BYTE-1 downto 0) of std_logic_vector(7 downto  0);
+   shared variable RAM_ODD        : ram_type_d64;
+   shared variable RAM_EVEN       : ram_type_d64;
+   
+   signal   page_d                : std_logic := '0';
+   signal   page_addr_clka        : std_logic := '0';
+   signal   page_addr_clkb        : std_logic_vector( 3 downto  0) := (others => '0');
+
+   attribute ASYNC_REG            : string;
+   attribute ASYNC_REG of page_addr_clkb : signal is "TRUE";
+   attribute DONT_TOUCH           : string;
+   attribute DONT_TOUCH of page_addr_clkb : signal is "TRUE";
+
+begin
+
+   -- Page switch command clka side
+   process (clka)
+   begin
+      if rising_edge(clka) then
+         page_d                   <= page;
+         if (page_d = '0' and page = '1') then
+            page_addr_clka        <= not page_addr_clka;
+         end if;
+      end if;
+   end process;
+
+   -- Page switch command clkb side
+   process (clkb)
+   begin
+      if rising_edge(clkb) then
+         page_addr_clkb           <= page_addr_clkb( 2 downto  0) & not page_addr_clka;
+      end if;
+   end process;
+   
+   -----------------------------------------------------------------------------
+   dob_32bit: if MEM_DOB_WIDTH = 32 generate
+   -----------------------------------------------------------------------------
+      process (clka)
+      begin
+         if rising_edge(clka) then
+            if (ena = '1') then
+               if (wea = '1') then
+                  RAM(conv_integer(page_addr_clka & addra)) := dia;
+               end if;
+            end if;
+         end if;
+      end process;
+      
+      process (clkb)
+      begin
+         if rising_edge(clkb) then
+            if (enb = '1') then
+               dob( 7 downto  0)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "00"));
+               dob(15 downto  8)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "01"));
+               dob(23 downto 16)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "10"));
+               dob(31 downto 24)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "11"));
+            end if;
+         end if;
+      end process;
+   end generate dob_32bit;
+   
+   -----------------------------------------------------------------------------
+   dob_64bit: if MEM_DOB_WIDTH = 64 generate
+   -----------------------------------------------------------------------------      
+      process (clka)
+      begin
+         if rising_edge(clka) then
+            if (ena = '1') then
+               if (wea = '1') then
+                  if (addra(0) = '1') then
+                     RAM_ODD (conv_integer(page_addr_clka & addra(addra'high downto 1))) := dia;
+                  else
+                     RAM_EVEN(conv_integer(page_addr_clka & addra(addra'high downto 1))) := dia;
+                  end if;
+               end if;
+            end if;
+         end if;
+      end process;
+      
+      process (clkb)
+      begin
+         if rising_edge(clkb) then
+            if (enb = '1') then
+               dob( 7 downto  0)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "00"));
+               dob(15 downto  8)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "00"));
+               dob(23 downto 16)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "01"));
+               dob(31 downto 24)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "01"));
+               dob(39 downto 32)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "10"));
+               dob(47 downto 40)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "10"));
+               dob(55 downto 48)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "11"));
+               dob(63 downto 56)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "11"));
+            end if;
+         end if;
+      end process;
+   end generate dob_64bit;
+
+end behavioral;
+
+
+--------------------------------------------------------------------------------
+-- End of file
+--------------------------------------------------------------------------------

hdl/evr320_dpram.vhd

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+--------------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+--------------------------------------------------------------------------------
+-- Unit    : evr320_dpram.vhd
+-- Author  : Waldemar Koprek, Section Diagnostic
+--           Goran Marinkovic, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Copyright<68> PSI, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Comment :
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.math_real.all;
+
+entity evr320_dpram is
+   generic 
+   (
+      MEM_SIZE_BYTE              : integer := 2048;
+      MEM_DOB_WIDTH              : integer := 32
+   );
+   port
+   (
+      -- port a
+      clka                        : in    std_logic;
+      ena                         : in    std_logic;
+      wea                         : in    std_logic;
+      addra                       : in    std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE))))-1 downto  0);
+      dia                         : in    std_logic_vector( 7 downto  0);
+      -- port b
+      clkb                        : in    std_logic;
+      enb                         : in    std_logic;
+      addrb                       : in    std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE/(MEM_DOB_WIDTH/8)))))-1 downto  0);
+      dob                         : out   std_logic_vector(MEM_DOB_WIDTH-1 downto  0)
+   );
+   
+   attribute ram_style                  : string;
+   attribute ram_style of evr320_dpram  : entity is "block";
+
+end evr320_dpram;
+
+architecture behavioral of evr320_dpram is
+
+   type ram_type_d32 is array (MEM_SIZE_BYTE-1 downto 0) of std_logic_vector(7 downto  0);
+   shared variable RAM            : ram_type_d32;
+   
+   type ram_type_d64 is array ((MEM_SIZE_BYTE/2)-1 downto 0) of std_logic_vector(7 downto  0);
+   shared variable RAM_ODD        : ram_type_d64;
+   shared variable RAM_EVEN       : ram_type_d64;
+
+begin
+
+   -----------------------------------------------------------------------------
+   dob_32bit: if MEM_DOB_WIDTH = 32 generate
+   -----------------------------------------------------------------------------
+      process (clka)
+      begin
+         if rising_edge(clka) then
+            if (ena = '1') then
+               if (wea = '1') then
+                  RAM(conv_integer(addra)) := dia;
+               end if;
+            end if;
+         end if;
+      end process;
+
+      process (clkb)
+      begin
+         if rising_edge(clkb) then
+            if (enb = '1') then
+               dob( 7 downto  0)     <= RAM(conv_integer(addrb & "00"));
+               dob(15 downto  8)     <= RAM(conv_integer(addrb & "01"));
+               dob(23 downto 16)     <= RAM(conv_integer(addrb & "10"));
+               dob(31 downto 24)     <= RAM(conv_integer(addrb & "11"));
+            end if;
+         end if;
+      end process;
+   end generate dob_32bit;
+      
+   -----------------------------------------------------------------------------
+   dob_64bit: if MEM_DOB_WIDTH = 64 generate
+   -----------------------------------------------------------------------------
+      process (clka)
+      begin
+         if rising_edge(clka) then
+            if (ena = '1') then
+               if (wea = '1') then
+                  if (addra(0) = '1') then
+                     RAM_ODD (conv_integer(addra(addra'high downto 1))) := dia;
+                  else
+                     RAM_EVEN(conv_integer(addra(addra'high downto 1))) := dia;
+                  end if;
+               end if;
+            end if;
+         end if;
+      end process;
+      
+      process (clkb)
+      begin
+         if rising_edge(clkb) then
+            if (enb = '1') then
+               dob( 7 downto  0)     <= RAM_EVEN(conv_integer(addrb & "00"));
+               dob(15 downto  8)     <= RAM_ODD (conv_integer(addrb & "00"));
+               dob(23 downto 16)     <= RAM_EVEN(conv_integer(addrb & "01"));
+               dob(31 downto 24)     <= RAM_ODD (conv_integer(addrb & "01"));
+               dob(39 downto 32)     <= RAM_EVEN(conv_integer(addrb & "10"));
+               dob(47 downto 40)     <= RAM_ODD (conv_integer(addrb & "10"));
+               dob(55 downto 48)     <= RAM_EVEN(conv_integer(addrb & "11"));
+               dob(63 downto 56)     <= RAM_ODD (conv_integer(addrb & "11"));
+            end if;
+         end if;
+      end process;
+   end generate dob_64bit;
+
+end behavioral;
+
+
+--------------------------------------------------------------------------------
+-- End of file
+--------------------------------------------------------------------------------

hdl/evr320_ifc1210_wrapper.vhd

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+ ---------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+-- ---------------------------------------------------------------------------
+-- Unit    : evr320_ifc1210_wrapper.vhd
+-- Author  : Patric Bucher
+-- ---------------------------------------------------------------------------
+-- Copyright© PSI, Section DSV
+-- ---------------------------------------------------------------------------
+-- Comment : 
+-- ---------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.math_real.all;
+
+use work.tosca2_glb_pkg.all;
+use work.evr320_pkg.all;
+use work.pkg_v6vlx_gtxe1.all;
+
+
+entity evr320_ifc1210_wrapper is
+  generic(
+    g_MGT_LOCATION                : string                        := "GTXE1_X0Y16";
+    g_REFCLK_MHZ                  : real                          := 142.8;
+    g_USE_MMCM                    : boolean                       := false;
+    g_EVENT_RECORDER              : boolean                       := false
+  );
+  port(
+    tick1sec_i                    : in    std_logic;      
+    -- ------------------------------------------------------------------------
+    -- Debug interface
+    -- ------------------------------------------------------------------------
+    debug_clk                     : out   std_logic;
+    debug                         : out   std_logic_vector(127 downto   0);
+    -- ------------------------------------------------------------------------
+    -- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
+    -- ------------------------------------------------------------------------
+    xuser_CLK                     : in    std_logic; 
+    xuser_RESET                   : in    std_logic;                    
+    xuser_TMEM_ENA                : in    std_logic;    
+    xuser_TMEM_WE                 : in    std_logic_vector( 7 downto 0);                  
+    xuser_TMEM_ADD                : in    std_logic_vector(13 downto 3); 
+    xuser_TMEM_DATW               : in    std_logic_vector(63 downto 0);
+    xuser_TMEM_DATR               : out   std_logic_vector(63 downto 0);
+    -- ------------------------------------------------------------------------
+    -- MGT Interface
+    -- ------------------------------------------------------------------------
+    mgt_refclk_i                  : in    std_logic;                         -- MGT Reference Clock
+    mgt_sfp_los_i                 : in    std_logic;                         -- SFP Loss of Signal (light on receiver)
+    mgt_rx_n                      : in    std_logic;                         -- MGT RX N
+    mgt_rx_p                      : in    std_logic;                         -- MGT RX P
+    mgt_tx_n                      : out   std_logic;                         -- MGT TX N
+    mgt_tx_p                      : out   std_logic;                         -- MGT TX P
+    mgt_status_o                  : out   std_logic_vector(31 downto 0);     -- MGT Status
+    mgt_control_i                 : in    std_logic_vector(31 downto 0);     -- MGT Control      
+    ---------------------------------------------------------------------------
+    -- User interface MGT clock
+    ---------------------------------------------------------------------------
+    clk_evr_o                     : out   std_logic;                         -- Recovered parallel clock from MGT
+    usr_events_o                  : out   std_logic_vector( 3 downto  0);    -- User defined event pulses with one clock cycle length
+    usr_events_ext_o              : out   std_logic_vector( 3 downto  0);    -- User defined event pulses with four clock cycle length
+    sos_event_o                   : out   std_logic                          -- Start-of-Sequence Event
+  );
+end evr320_ifc1210_wrapper;
+
+
+architecture rtl of evr320_ifc1210_wrapper is
+
+  -- --------------------------------------------------------------------------
+  -- Parameters
+  -- --------------------------------------------------------------------------
+  -- constant c_BYTE                         : integer := 8;
+  constant c_TOSCA2_DATA_WIDTH            : integer := 64;
+  -- constant c_EVR_REG64_COUNT              : integer := 16;
+  -- constant c_EVR_MEM_SIZE                 : integer := 16384;
+  -- constant c_EVR_ADDR_WIDTH               : integer := integer(ceil(log2(real(c_EVR_MEM_SIZE/(c_TOSCA2_DATA_WIDTH/c_BYTE)))));
+  
+
+  -- --------------------------------------------------------------------------
+  -- Signal definitions
+  -- --------------------------------------------------------------------------
+  signal clk_evr                          : std_logic;
+--signal clk_evr_monitor                  : std_logic; -- for debugging
+  signal rst_evr                          : std_logic;
+  
+  signal mgt_control                      : std_logic_vector(31 downto 0)                   := (others => '0');
+  signal mgt_control_sync                 : std_logic_vector(31 downto 0)                   := (others => '0');
+  signal mgt_control_sync2                : std_logic_vector(31 downto 0)                   := (others => '0');
+  signal mgt_sfp_los                      : std_logic                                       := '0';
+  signal mgt_sfp_los_sync                 : std_logic                                       := '0';
+  
+  signal mgt_status                       : std_logic_vector(31 downto  0);
+
+  signal mgt_rx_data                      : std_logic_vector(15 downto  0);
+  signal mgt_rx_charisk                   : std_logic_vector( 1 downto  0);
+  signal mgt_lossofsync                   : std_logic;
+  
+  signal mgt_reset_tmem_evr               : std_logic; -- for legacy reasons, ifc1210 mgt control is in tmem_psi_generic part
+  signal mgt_reset_tmem_evr_sync1         : std_logic := '0'; 
+  signal mgt_reset_tmem_evr_sync2         : std_logic := '0'; 
+  
+  signal mem_clk                          : std_logic;
+  signal mem_addr_evr                     : std_logic_vector(11 downto 0);  
+  signal mem_addr_tosca                   : std_logic_vector(10 downto 0); 
+  signal mem_data                         : std_logic_vector(c_TOSCA2_DATA_WIDTH-1 downto 0);
+  
+  signal evr_params                       : typ_evr320_params;
+  signal event_recorder_status            : typ_evt_rec_status;
+  signal event_recorder_control           : typ_evt_rec_ctrl;
+  
+  signal evr_counter_rst                  : std_logic_vector( 2 downto 0) := (others => '0');
+  signal evr_clk_counter                  : std_logic_vector(31 downto 0) := (others => '0');
+  signal evr_frequency                    : std_logic_vector(31 downto 0) := (others => '0');
+  
+  signal debug_data                       : std_logic_vector(127 downto 0);
+
+
+  -- --------------------------------------------------------------------------
+  -- Attribute definitions
+  -- --------------------------------------------------------------------------
+  attribute keep                          : string;
+  attribute keep of clk_evr               : signal is "TRUE"; 
+  attribute keep of debug_data            : signal is "TRUE";
+  
+  
+  
+-- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+-- ////////////////////           Main Body           /////////////////////////
+-- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+begin
+
+  -- --------------------------------------------------------------------------
+  -- static signal assignments
+  -- --------------------------------------------------------------------------
+  mgt_lossofsync                  <= mgt_status(15);
+  rst_evr                         <= mgt_status(15);
+  mem_addr_evr                    <= '0' & mem_addr_tosca;
+
+  mgt_control(c_GTXRESET)         <= mgt_control_i(c_GTXRESET) or mgt_sfp_los_i or mgt_reset_tmem_evr;
+  mgt_control( 4 downto 1)        <= mgt_control_i( 4 downto 1);
+  mgt_control(c_RXCDRRESET)       <= mgt_control_i(c_RXCDRRESET);
+  mgt_control(31 downto 6)        <= mgt_control_i(31 downto 6);
+      
+  -- --------------------------------------------------------------------------
+  -- Synchronisation to EVR Clock
+  -- --------------------------------------------------------------------------
+  -- prc_sync_evr: process(clk_evr)
+  -- begin
+    -- if rising_edge(clk_evr) then
+      -- --- 
+      -- -- mgt_sfp_los_sync            <= mgt_sfp_los_i;
+      -- -- mgt_sfp_los                 <= mgt_sfp_los_sync;
+      -- --- 
+      -- -- mgt_control_sync            <= mgt_control_i;
+      -- -- mgt_control_sync2           <= mgt_control_sync;
+      -- --- 
+      -- -- mgt_reset_tmem_evr_sync1    <= mgt_reset_tmem_evr;    
+      -- -- mgt_reset_tmem_evr_sync2    <= mgt_reset_tmem_evr_sync1;    
+      -- --- 
+      -- -- evr_params and event_recorder_control add sync here or in evr320_decoder
+      -- --- 
+      -- -- mgt_control(c_GTXRESET)     <= mgt_control_sync2(c_GTXRESET);
+      -- -- -- mgt_control(c_GTXRESET)     <= mgt_control_sync2(c_GTXRESET) or mgt_sfp_los or mgt_reset_tmem_evr_sync2;
+      -- -- mgt_control( 4 downto 1)    <= mgt_control_sync2( 4 downto 1);
+      -- -- mgt_control(c_RXCDRRESET)   <= mgt_control_sync2(c_RXCDRRESET);
+      -- -- mgt_control(31 downto 6)    <= mgt_control_sync2(31 downto 6);
+      -- ---
+    -- end if;
+  -- end process;
+  
+
+  -- --------------------------------------------------------------------------
+  -- EVR320 Decoder
+  -- --------------------------------------------------------------------------
+  evr320_decoder_inst: entity work.evr320_decoder
+    generic map(
+      EVENT_RECORDER              => g_EVENT_RECORDER,
+      MEM_DATA_WIDTH              => c_TOSCA2_DATA_WIDTH )
+    port map(
+      -- Debug interface
+      debug_clk                   => debug_clk,
+      debug                       => debug_data,
+      -- GTX parallel interface
+      i_mgt_rst                   => mgt_lossofsync,
+      i_mgt_rx_clk                => clk_evr,
+      i_mgt_rx_data               => mgt_rx_data,
+      i_mgt_rx_charisk            => mgt_rx_charisk,
+      -- User interface CPU clock
+      i_usr_clk                   => mem_clk,
+      i_evr_params                => evr_params,
+      o_event_recorder_stat       => event_recorder_status,
+      i_event_recorder_ctrl       => event_recorder_control,
+      i_mem_addr                  => mem_addr_evr,
+      o_mem_data                  => mem_data,
+      -- User interface MGT clock
+      o_usr_events                => usr_events_o,
+      o_usr_events_ext            => usr_events_ext_o,
+      o_sos_event                 => sos_event_o
+   );
+   
+
+  -- --------------------------------------------------------------------------
+  -- MGT Wrapper for GTX Virtex-6
+  -- --------------------------------------------------------------------------
+  mgt_wrapper_inst: entity work.v6vlx_gtxe1_wrapper
+    generic map(
+      g_MGT_LOCATION              => g_MGT_LOCATION,
+      g_USE_MMCM                  => g_USE_MMCM )
+    port map(   
+      -- MGT serial interface   
+      i_mgt_refclk                => mgt_refclk_i,
+      o_mgt_refclk                => open,
+      i_mgt_rx_p                  => mgt_rx_p,
+      i_mgt_rx_n                  => mgt_rx_n,
+      o_mgt_tx_p                  => mgt_tx_p,
+      o_mgt_tx_n                  => mgt_tx_n,
+      -- MGT parallel interface   
+      o_mgt_status                => mgt_status,
+      i_mgt_control               => mgt_control,
+      o_mgt_recclk                => clk_evr,
+      o_mgt_rx_data               => mgt_rx_data,
+      o_mgt_rx_charisk            => mgt_rx_charisk
+    );
+  
+
+  -- --------------------------------------------------------------------------
+  -- TMEM 
+  -- --------------------------------------------------------------------------  
+  evr320_tmem_inst: entity work.evr320_tmem
+  port map(
+    -- TOSCA2 TMEM Interface 
+    xuser_CLK                     => xuser_CLK,         
+    xuser_RESET                   => xuser_RESET,       
+    xuser_TMEM_ENA                => xuser_TMEM_ENA,    
+    xuser_TMEM_WE                 => xuser_TMEM_WE,        
+    xuser_TMEM_ADD                => xuser_TMEM_ADD,    
+    xuser_TMEM_DATW               => xuser_TMEM_DATW,   
+    xuser_TMEM_DATR               => xuser_TMEM_DATR,   
+    -- EVR320 Memory/Parameter Interface
+    evr_params_o                  => evr_params,
+    evr_frequency_i               => evr_frequency,
+    evr_evt_rec_status_i          => event_recorder_status,
+    evr_evt_rec_control_o         => event_recorder_control,
+    mgt_status_i                  => mgt_status,        
+    mgt_reset_o                   => mgt_reset_tmem_evr,          
+    mem_clk_o                     => mem_clk,
+    mem_addr_o                    => mem_addr_tosca,
+    mem_data_i                    => mem_data
+  );
+  
+
+  -- --------------------------------------------------------------------------
+  -- Measure EVR Clock (based on xuser_CLK)
+  -- --------------------------------------------------------------------------
+  prc_count_cycles: process(clk_evr)
+  begin
+    if rising_edge(clk_evr) then      
+      if (evr_counter_rst(2 downto 1) = "01") then
+        evr_frequency               <= evr_clk_counter;
+        evr_clk_counter             <= (others => '0');
+      else
+        evr_clk_counter             <= evr_clk_counter + X"0000_0001";
+      end if;
+      -- sync reset and detect edge
+      evr_counter_rst <= evr_counter_rst(1 downto 0) & tick1sec_i;
+    end if;
+  end process;
+
+
+  -- --------------------------------------------------------------------------
+  -- port mapping
+  -- --------------------------------------------------------------------------
+  clk_evr_o               <= clk_evr;
+  mgt_status_o            <= mgt_status;
+  debug                   <= debug_data;
+
+
+  
+end rtl;
+-- ----------------------------------------------------------------------------
+-- ////////////////////////////////////////////////////////////////////////////
+-- ----------------------------------------------------------------------------

hdl/evr320_pkg.vhd

@@ -0,0 +1,98 @@
+--------------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+--------------------------------------------------------------------------------
+-- Unit    : evr320_pkg.vhd
+-- Author  : Waldemar Koprek, Section Diagnostic
+--           Goran Marinkovic, Section Diagnostic
+--           Patric Bucher, Section DSV
+--------------------------------------------------------------------------------
+-- Copyright<68> PSI, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Comment : Definitions and Types used for the evr320 library component.
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+package evr320_pkg is
+
+  -- --------------------------------------------------------------------------
+  -- Constants                                                    
+  -- --------------------------------------------------------------------------
+  constant c_CHECKSUM_MIN_EVT     : std_logic_vector(31 downto 0)   := X"00000064"; -- Check sum min count for events 100
+  constant c_CHECKSUM_MIN_TIME    : std_logic_vector(31 downto 0)   := X"0015CA20"; -- Check sum min time for events 10 ms
+  constant c_SOS_EVENT_DEFAULT    : std_logic_vector( 7 downto 0)   := X"20";       -- decimal 32
+  
+
+  -- --------------------------------------------------------------------------
+  -- Type Definitions                                                      
+  -- --------------------------------------------------------------------------
+  type typ_arr8  is array (natural range <>) of std_logic_vector(7 downto 0);
+  
+  type typ_evr320_params is record
+    event_numbers               : typ_arr8( 3 downto  0);
+    event_enable                : std_logic_vector( 3 downto  0);
+    cs_min_cnt                  : std_logic_vector(31 downto  0);
+    cs_min_time                 : std_logic_vector(31 downto  0);
+  end record typ_evr320_params;
+  
+  type typ_evr320_status is record
+    mgt_status                  : std_logic_vector(31 downto  0);
+  end record typ_evr320_status;
+  
+  type typ_evt_rec_status is record
+    data_valid                  : std_logic;
+    data_error                  : std_logic;
+    usr_events_counter          : std_logic_vector(31 downto  0);
+  end record typ_evt_rec_status;
+  
+  type typ_evt_rec_ctrl is record
+    event_number                : std_logic_vector( 7 downto  0);
+    event_enable                : std_logic;
+    data_ack                    : std_logic;
+    error_ack                   : std_logic;
+  end record typ_evt_rec_ctrl;
+  
+  
+  -- --------------------------------------------------------------------------
+  -- Type Initialisation                                                      
+  -- --------------------------------------------------------------------------
+  constant c_INIT_EVT_REC_STATUS : typ_evt_rec_status :=  ( data_valid          => '0',
+                                                            data_error          => '0',
+                                                            usr_events_counter  => (others =>'0'));
+                                                            
+                                                            
+  -- --------------------------------------------------------------------------
+  -- Function Prototypes
+  -- --------------------------------------------------------------------------
+  function bit2byte(bit_zero : std_logic) return std_logic_vector; 
+  function bit2byte(bit_zero_vec : std_logic_vector) return std_logic_vector; 
+
+  
+end package evr320_pkg;
+--------------------------------------------------------------------------------
+package body evr320_pkg is
+
+  -- ------------------------------------------------------------------------
+  -- Functions
+  -- ------------------------------------------------------------------------
+  -- Bit Zero to Byte Conversion (concat with zeros)
+  function bit2byte(bit_zero : std_logic) return std_logic_vector is
+  begin
+    return B"0000_000" & bit_zero;
+  end function;  
+  
+  function bit2byte(bit_zero_vec : std_logic_vector) return std_logic_vector is
+    variable converted_byte_vec : std_logic_vector(8*bit_zero_vec'length-1 downto 0);
+  begin
+    for i in 0 to bit_zero_vec'length-1 loop
+      converted_byte_vec(i*8+7 downto i*8) := B"0000_000" & bit_zero_vec(bit_zero_vec'low + i);
+    end loop;
+    return converted_byte_vec;
+  end function;
+
+
+
+end package body evr320_pkg;
+--------------------------------------------------------------------------------
+-- End of file
+--------------------------------------------------------------------------------

hdl/evr320_timestamp.vhd

@@ -0,0 +1,159 @@
+--------------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+--------------------------------------------------------------------------------
+-- Unit    : evr320_timestamp.vhd
+-- Author  : Patric Bucher, Section DSV
+--           Goran Marinkovic, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Copyright<68> PSI, Section Diagnostic
+--------------------------------------------------------------------------------
+-- Comment :
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.math_real.all;
+
+
+entity evr320_timestamp is
+   generic 
+   (
+      MEM_SIZE_BYTE              : integer := 2048;
+      MEM_DOB_WIDTH              : integer := 32
+   );
+   port
+   (
+      -- port a
+      clka                        : in    std_logic;
+      ena                         : in    std_logic;
+      wea                         : in    std_logic;
+      addra                       : in    std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE/4))))-1 downto  0);
+      dia                         : in    std_logic_vector(31 downto  0);
+      page                        : in    std_logic;
+      -- port b
+      clkb                        : in    std_logic;
+      enb                         : in    std_logic;
+      addrb                       : in    std_logic_vector(integer(ceil(log2(real(MEM_SIZE_BYTE/(MEM_DOB_WIDTH/8)))))-1 downto  0);
+      dob                         : out   std_logic_vector(MEM_DOB_WIDTH-1 downto  0)
+   );
+   
+   attribute ram_style                         : string;
+   attribute ram_style of evr320_timestamp     : entity is "block";
+   
+end evr320_timestamp;
+
+architecture behavioral of evr320_timestamp is
+
+   type ram_type_d32 is array ((2*MEM_SIZE_BYTE)-1 downto 0) of std_logic_vector( 7 downto  0);
+   shared variable RAM            : ram_type_d32;
+   
+   type ram_type_d64 is array (MEM_SIZE_BYTE-1 downto 0) of std_logic_vector(7 downto  0);
+   shared variable RAM_ODD        : ram_type_d64;
+   shared variable RAM_EVEN       : ram_type_d64;
+   
+   signal   page_d                : std_logic_vector( 1 downto  0) := (others => '0');
+   signal   page_addr_clka        : std_logic := '0';
+   signal   page_addr_clkb        : std_logic_vector( 3 downto  0) := (others => '0');
+
+   attribute ASYNC_REG            : string;
+   attribute ASYNC_REG of page_addr_clkb : signal is "TRUE";
+   attribute DONT_TOUCH           : string;
+   attribute DONT_TOUCH of page_addr_clkb : signal is "TRUE";
+
+begin
+
+   -- Page switch command clka side
+   process (clka)
+   begin
+      if rising_edge(clka) then
+         page_d                   <= page_d( 0) & page;
+      end if;
+   end process;
+
+   process (clka)
+   begin
+      if rising_edge(clka) then
+         if (page_d = "01") then
+            page_addr_clka        <= not page_addr_clka;
+         end if;
+      end if;
+   end process;
+
+   -- Page switch command clkb side
+   process (clkb)
+   begin
+      if rising_edge(clkb) then
+         page_addr_clkb           <= page_addr_clkb( 2 downto  0) & not page_addr_clka;
+      end if;
+   end process;
+
+   -----------------------------------------------------------------------------
+   dob_32bit: if MEM_DOB_WIDTH = 32 generate
+   -----------------------------------------------------------------------------
+      process (clka)
+      begin
+         if rising_edge(clka) then
+            if (ena = '1') then
+               if (wea = '1') then
+                  RAM(conv_integer(page_addr_clka & addra & "00")) := dia( 7 downto  0);
+                  RAM(conv_integer(page_addr_clka & addra & "01")) := dia(15 downto  8);
+                  RAM(conv_integer(page_addr_clka & addra & "10")) := dia(23 downto 16);
+                  RAM(conv_integer(page_addr_clka & addra & "11")) := dia(31 downto 24);
+               end if;
+            end if;
+         end if;
+      end process;
+   
+      process (clkb)
+      begin
+         if rising_edge(clkb) then
+            if (enb = '1') then
+               dob( 7 downto  0)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "00"));
+               dob(15 downto  8)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "01"));
+               dob(23 downto 16)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "10"));
+               dob(31 downto 24)     <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "11"));
+            end if;
+         end if;
+      end process;
+   end generate dob_32bit;
+   
+   -----------------------------------------------------------------------------
+   dob_64bit: if MEM_DOB_WIDTH = 64 generate
+   -----------------------------------------------------------------------------
+      process (clka)
+      begin
+         if rising_edge(clka) then
+            if (ena = '1') then
+               if (wea = '1') then
+                  RAM_EVEN(conv_integer(page_addr_clka & addra & '0')) := dia( 7 downto  0);
+                  RAM_ODD (conv_integer(page_addr_clka & addra & '0')) := dia(15 downto  8);
+                  RAM_EVEN(conv_integer(page_addr_clka & addra & '1')) := dia(23 downto 16);
+                  RAM_ODD (conv_integer(page_addr_clka & addra & '1')) := dia(31 downto 24);
+               end if;
+            end if;
+         end if;
+      end process;
+      
+      process (clkb)
+      begin
+         if rising_edge(clkb) then
+            if (enb = '1') then
+               dob( 7 downto  0)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "00"));
+               dob(15 downto  8)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "00"));
+               dob(23 downto 16)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "01"));
+               dob(31 downto 24)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "01"));
+               dob(39 downto 32)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "10"));
+               dob(47 downto 40)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "10"));
+               dob(55 downto 48)     <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "11"));
+               dob(63 downto 56)     <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "11"));
+            end if;
+         end if;
+      end process;
+   end generate dob_64bit;
+
+end behavioral;
+
+
+--------------------------------------------------------------------------------
+-- End of file
+--------------------------------------------------------------------------------

hdl/evr320_tmem.vhd

@@ -0,0 +1,257 @@
+-- ---------------------------------------------------------------------------
+--                       Paul Scherrer Institute (PSI)
+-- ---------------------------------------------------------------------------
+-- Unit    : evr320_tmem.vhd
+-- Author  : Patric Bucher
+-- ---------------------------------------------------------------------------
+-- Copyright© PSI, Section DSV
+-- ---------------------------------------------------------------------------
+-- Comment : 
+-- ---------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+use work.tosca2_glb_pkg.all;
+use work.evr320_pkg.all;
+
+
+entity evr320_tmem is
+  port(
+    -- ------------------------------------------------------------------------
+    -- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
+    -- ------------------------------------------------------------------------
+    xuser_CLK                     : in    std_logic; 
+    xuser_RESET                   : in    std_logic;                    
+    xuser_TMEM_ENA                : in    std_logic;    
+    xuser_TMEM_WE                 : in    std_logic_vector( 7 downto 0);                  
+    xuser_TMEM_ADD                : in    std_logic_vector(13 downto 3); 
+    xuser_TMEM_DATW               : in    std_logic_vector(63 downto 0);
+    xuser_TMEM_DATR               : out   std_logic_vector(63 downto 0);
+    ---------------------------------------------------------------------------
+    -- EVR320 Memory/Parameter Interface
+    ---------------------------------------------------------------------------
+    evr_params_o                  : out   typ_evr320_params;
+    evr_frequency_i               : in    std_logic_vector(31 downto  0);
+    evr_evt_rec_status_i          : in    typ_evt_rec_status;           
+    evr_evt_rec_control_o         : out   typ_evt_rec_ctrl;           
+    mgt_status_i                  : in    std_logic_vector(31 downto  0);          
+    mgt_reset_o                   : out   std_logic;          
+    mem_clk_o                     : out   std_logic; 
+    mem_addr_o                    : out   std_logic_vector(10 downto  0); 
+    mem_data_i                    : in    std_logic_vector(63 downto  0)
+  );
+end evr320_tmem;
+
+
+architecture rtl of evr320_tmem is
+
+ -- ---------------------------------------------------------------------------
+  -- Constants
+  -- ---------------------------------------------------------------------------
+  constant reserved               : std_logic_vector(63 downto  0)   := X"0000_0000_0000_0000";
+  constant NUM_REG64              : integer := 16;
+  constant TMEM_ADDR_LSB          : integer := 3; -- 64 bit
+  constant REG_ADDR_WIDTH         : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
+  constant REG_ADDR_MSB           : integer := REG_ADDR_WIDTH - 1;
+  constant MEM_ADDR_START         : std_logic_vector(7 downto  0) := X"10";
+  
+
+  
+  -- --------------------------------------------------------------------------
+  -- Signal definitions
+  -- --------------------------------------------------------------------------
+  -- xuser tmem signals
+  signal xuser_TMEM_WE_reg      : std_logic_vector( 7 downto 0)   := (others => '0');
+  signal xuser_TMEM_ENA_reg     : std_logic                       := '0';
+  signal xuser_TMEM_ADD_reg     : std_logic_vector(13 downto 3)   := (others => '0');
+  signal xuser_TMEM_DATW_reg    : std_logic_vector(63 downto 0)   := (others => '0');
+  
+  -- evr params
+  signal mgt_status_evr         : std_logic_vector(15 downto 0)   := (others => '0');
+  signal mgt_status_evr_sync    : std_logic_vector(15 downto 0)   := (others => '0');
+  signal mgt_reset              : std_logic                       := '0';
+  signal event_enable           : std_logic_vector( 3 downto 0)   := (others => '0');
+  signal event_numbers          : typ_arr8(3 downto 0)            := (others => (others => '0'));
+  signal event_numbers_concat   : std_logic_vector(31 downto 0);
+  signal cs_min_cnt             : std_logic_vector(31 downto 0)   := c_CHECKSUM_MIN_EVT;
+  signal cs_min_time            : std_logic_vector(31 downto 0)   := c_CHECKSUM_MIN_TIME;
+  signal evr_frequency_sync     : std_logic_vector(31 downto 0)   := (others => '0');
+  signal evr_frequency          : std_logic_vector(31 downto 0)   := (others => '0');
+  
+  -- event recorder    
+  signal er_status              : typ_evt_rec_status              := c_INIT_EVT_REC_STATUS;
+  signal er_status_sync         : typ_evt_rec_status              := c_INIT_EVT_REC_STATUS;
+  signal er_event_enable        : std_logic                       := '0';
+  signal er_event_number        : std_logic_vector( 7 downto 0)   := c_SOS_EVENT_DEFAULT;
+  signal er_data_ack            : std_logic_vector( 3 downto 0)   := (others => '0');
+  signal er_error_ack           : std_logic_vector( 3 downto 0)   := (others => '0');
+  signal er_handshake_status    : std_logic_vector(31 downto 0)   := (others => '0');
+  signal er_control_concat      : std_logic_vector(31 downto 0)   := (others => '0');
+
+  -- signal evr_force              : std_logic_vector(3 downto 0)    := (others => '0');
+  -- signal evr_force_rd           : std_logic_vector(3 downto 0)    := (others => '0');  -- readback
+  -- signal evr_force_pulse        : typ_arr4(3 downto 0)            := (others => (others => '0'));
+  
+  
+
+-- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+-- ////////////////////           Main Body           /////////////////////////
+-- ----------------------------------------------------------------------------
+-- ----------------------------------------------------------------------------
+begin
+
+  -- --------------------------------------------------------------------------
+  -- static signal assignments                                                      
+  -- --------------------------------------------------------------------------
+  event_numbers_concat  <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0);
+  er_handshake_status   <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid);
+  er_control_concat     <= X"0000" & er_event_number & bit2byte(er_event_enable);
+
+  
+  -- --------------------------------------------------------------------------
+  -- Synchronisation to xuser_CLK                                                      
+  -- --------------------------------------------------------------------------
+  prc_sync_xuser: process (xuser_CLK)
+  begin
+    if rising_edge(xuser_CLK) then
+      ---
+      xuser_TMEM_WE_reg     <= xuser_TMEM_WE;
+      xuser_TMEM_ENA_reg    <= xuser_TMEM_ENA; 
+      xuser_TMEM_DATW_reg   <= xuser_TMEM_DATW;
+      xuser_TMEM_ADD_reg    <= xuser_TMEM_ADD;
+      ---
+      mgt_status_evr_sync   <= "000000" & mgt_status_i(c_RXRESETDONE) & mgt_status_i(c_RXLOSSOFSYNC) & "000000" & mgt_status_i(c_RXRESETDONE) & mgt_status_i(c_RXPLLLKDET);
+      mgt_status_evr        <= mgt_status_evr_sync;
+      ---
+      er_status_sync        <= evr_evt_rec_status_i;
+      er_status             <= er_status_sync;
+      ---
+      evr_frequency_sync    <= evr_frequency_i;
+      evr_frequency         <= evr_frequency_sync;
+      ---
+    end if;
+  end process;
+
+  
+  -- --------------------------------------------------------------------------
+  -- Read operation                                                       
+  -- --------------------------------------------------------------------------
+  read_tmem_evr: process(xuser_CLK)
+  begin
+    if (rising_edge(xuser_CLK)) then
+      if (xuser_TMEM_ENA_reg = '1') then
+        if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0) then
+          case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
+            when X"0" =>    xuser_TMEM_DATR <=  event_numbers_concat          & X"0000" & mgt_status_evr;           -- 64bit / ByteAddr 000
+            when X"1" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)        & X"0000_00" & bit2byte(mgt_reset);   -- 64bit / ByteAddr 008   --> 0x00C = not implemented in ifc1210
+            when X"2" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)        & bit2byte(event_enable);             -- 64bit / ByteAddr 010   --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ...  evr_force
+            when X"3" =>    xuser_TMEM_DATR <=  evr_frequency                 & reserved(31 downto 0);              -- 64bit / ByteAddr 018   --> 0x018 = Implementation Options + c_EVR_Location_vec 
+            when X"4" =>    xuser_TMEM_DATR <=  cs_min_time                   & cs_min_cnt;                         -- 64bit / ByteAddr 020
+            when X"5" =>    xuser_TMEM_DATR <=  reserved(63 downto 0);                                              -- 64bit / ByteAddr 028
+            when X"6" =>    xuser_TMEM_DATR <=  reserved(63 downto 0);                                              -- 64bit / ByteAddr 030
+            when X"7" =>    xuser_TMEM_DATR <=  reserved(63 downto 0);                                              -- 64bit / ByteAddr 038
+            when X"8" =>    xuser_TMEM_DATR <=  er_handshake_status           & er_control_concat;                  -- 64bit / ByteAddr 040                
+            when X"9" =>    xuser_TMEM_DATR <=  reserved(63 downto 32)        & er_status.usr_events_counter;       -- 64bit / ByteAddr 048   
+            when others =>  xuser_TMEM_DATR <=  (others => '0');
+          end case;
+        else --> 0x0080-0x4000
+          xuser_TMEM_DATR <= mem_data_i;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  
+  -- --------------------------------------------------------------------------
+  -- Write operation  - Byte control                                           
+  -- --------------------------------------------------------------------------
+  write_tmem_evr: process(xuser_CLK)
+  begin
+    if rising_edge(xuser_CLK) then
+    
+      -- default assignments
+      er_data_ack   <= er_data_ack(2 downto 0) & '0';
+      er_error_ack  <= er_error_ack(2 downto 0) & '0';
+
+      
+      if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0)  then
+        -----------------------------------------------------------------------------------------------------------------
+        if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
+       -- if xuser_TMEM_WE_reg(0) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
+       -- if xuser_TMEM_WE_reg(1) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg(15 downto  8); end if;
+       -- if xuser_TMEM_WE_reg(2) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg(23 downto 16); end if;
+       -- if xuser_TMEM_WE_reg(3) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg(31 downto 24); end if;
+          if xuser_TMEM_WE_reg(4) = '1' then event_numbers(0)               <= xuser_TMEM_DATW_reg(39 downto 32); end if;
+          if xuser_TMEM_WE_reg(5) = '1' then event_numbers(1)               <= xuser_TMEM_DATW_reg(47 downto 40); end if;
+          if xuser_TMEM_WE_reg(6) = '1' then event_numbers(2)               <= xuser_TMEM_DATW_reg(55 downto 48); end if;
+          if xuser_TMEM_WE_reg(7) = '1' then event_numbers(3)               <= xuser_TMEM_DATW_reg(63 downto 56); end if;
+        end if;
+        -----------------------------------------------------------------------------------------------------------------
+        if xuser_TMEM_ADD_reg(6 downto 3) = X"1" then --ByteAddr 008
+          if xuser_TMEM_WE_reg(0) = '1' then mgt_reset                      <= xuser_TMEM_DATW_reg(0); end if; 
+       -- if xuser_TMEM_WE_reg(1) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(15 downto  8); end if;
+       -- if xuser_TMEM_WE_reg(2) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(23 downto 16); end if;
+       -- if xuser_TMEM_WE_reg(3) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(31 downto 24); end if;
+       -- if xuser_TMEM_WE_reg(4) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(39 downto 32); end if;
+       -- if xuser_TMEM_WE_reg(5) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(47 downto 40); end if;
+       -- if xuser_TMEM_WE_reg(6) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(55 downto 48); end if;
+       -- if xuser_TMEM_WE_reg(7) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(63 downto 56); end if;
+        end if;
+        -----------------------------------------------------------------------------------------------------------------
+        if xuser_TMEM_ADD_reg(6 downto 3) = X"2" then --ByteAddr 010
+          if xuser_TMEM_WE_reg(0) = '1' then event_enable(0)                <= xuser_TMEM_DATW_reg( 0); end if; 
+          if xuser_TMEM_WE_reg(1) = '1' then event_enable(1)                <= xuser_TMEM_DATW_reg( 8); end if;
+          if xuser_TMEM_WE_reg(2) = '1' then event_enable(2)                <= xuser_TMEM_DATW_reg(16); end if;
+          if xuser_TMEM_WE_reg(3) = '1' then event_enable(3)                <= xuser_TMEM_DATW_reg(24); end if;
+       -- if xuser_TMEM_WE_reg(4) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(39 downto 32); end if;
+       -- if xuser_TMEM_WE_reg(5) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(47 downto 40); end if;
+       -- if xuser_TMEM_WE_reg(6) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(55 downto 48); end if;
+       -- if xuser_TMEM_WE_reg(7) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(63 downto 56); end if;
+        end if;
+        -----------------------------------------------------------------------------------------------------------------
+        if xuser_TMEM_ADD_reg(6 downto 3) = X"4" then --ByteAddr 020
+          if xuser_TMEM_WE_reg(0) = '1' then cs_min_cnt ( 7 downto  0)      <= xuser_TMEM_DATW_reg( 7 downto  0); end if; 
+          if xuser_TMEM_WE_reg(1) = '1' then cs_min_cnt (15 downto  8)      <= xuser_TMEM_DATW_reg(15 downto  8); end if;
+          if xuser_TMEM_WE_reg(2) = '1' then cs_min_cnt (23 downto 16)      <= xuser_TMEM_DATW_reg(23 downto 16); end if;
+          if xuser_TMEM_WE_reg(3) = '1' then cs_min_cnt (31 downto 24)      <= xuser_TMEM_DATW_reg(31 downto 24); end if;
+          if xuser_TMEM_WE_reg(4) = '1' then cs_min_time( 7 downto  0)      <= xuser_TMEM_DATW_reg(39 downto 32); end if;
+          if xuser_TMEM_WE_reg(5) = '1' then cs_min_time(15 downto  8)      <= xuser_TMEM_DATW_reg(47 downto 40); end if;
+          if xuser_TMEM_WE_reg(6) = '1' then cs_min_time(23 downto 16)      <= xuser_TMEM_DATW_reg(55 downto 48); end if;
+          if xuser_TMEM_WE_reg(7) = '1' then cs_min_time(31 downto 24)      <= xuser_TMEM_DATW_reg(63 downto 56); end if;
+        end if;
+        -----------------------------------------------------------------------------------------------------------------
+        if xuser_TMEM_ADD_reg(6 downto 3) = X"8" then --ByteAddr 040
+          if xuser_TMEM_WE_reg(0) = '1' then er_event_enable                <= xuser_TMEM_DATW_reg(0); end if; 
+          if xuser_TMEM_WE_reg(1) = '1' then er_event_number                <= xuser_TMEM_DATW_reg(15 downto  8); end if;
+       -- if xuser_TMEM_WE_reg(2) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(23 downto 16); end if;
+       -- if xuser_TMEM_WE_reg(3) = '1' then  -reserved-                    <= xuser_TMEM_DATW_reg(31 downto 24); end if;
+       -- if xuser_TMEM_WE_reg(4) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg(39 downto 32); end if;
+       -- if xuser_TMEM_WE_reg(5) = '1' then  -read only-                   <= xuser_TMEM_DATW_reg(47 downto 40); end if;
+          if xuser_TMEM_WE_reg(6) = '1' and xuser_TMEM_DATW_reg(48) = '1' then er_data_ack    <= (others => '1'); end if;
+          if xuser_TMEM_WE_reg(7) = '1' and xuser_TMEM_DATW_reg(56) = '1' then er_error_ack   <= (others => '1'); end if;
+        end if;
+        -----------------------------------------------------------------------------------------------------------------
+      end if;
+    end if;
+  end process;
+  
+  
+  -- --------------------------------------------------------------------------
+  -- Port mapping                                                       
+  -- --------------------------------------------------------------------------
+  mem_clk_o               <= xuser_CLK;
+  mem_addr_o              <= xuser_TMEM_ADD - MEM_ADDR_START;
+  evr_params_o            <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
+  evr_evt_rec_control_o   <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
+  mgt_reset_o             <= mgt_reset;
+  
+
+  
+end rtl;
+-- ----------------------------------------------------------------------------
+-- ////////////////////////////////////////////////////////////////////////////
+-- ----------------------------------------------------------------------------

sim/ci.do

@@ -0,0 +1,2 @@
+source run.tcl
+quit

sim/ciFlow.py

@@ -0,0 +1,16 @@
+import os
+
+os.system("vsim -c -do ci.do")
+
+with open("Transcript.transcript") as f:
+	content = f.read()
+	
+#Expected Errors
+if "###ERROR###" in content:
+	exit(-1)
+#Unexpected Errors
+if "SIMULATIONS COMPLETED SUCCESSFULLY" not in content:
+	exit(-2)
+#Success
+else:
+	exit(0)

sim/config.tcl

@@ -0,0 +1,34 @@
+#Constants
+set LibPath "../../.."
+
+#Import psi::sim library
+namespace import psi::sim::*
+
+#Set library
+add_library evr320
+
+#suppress messages
+compile_suppress 135,1236
+run_suppress 8684,3479,3813,8009,3812
+
+
+# EVR320 Library
+add_sources $LibPath/VHDL/evr320/hdl {
+	evr320_pkg.vhd \
+	evr320_buffer.vhd \
+	evr320_dpram.vhd \
+	evr320_timestamp.vhd \
+	evr320_decoder.vhd \
+} -tag lib
+
+# Lib tosca2 dependecies
+add_sources $LibPath/BoardSupport/IFC1210/tosca2/hdl/top_ip/src/ {
+  tosca2_glb_pkg.vhd \
+} -tag tosca2
+
+# Lib ifc1210
+add_sources $LibPath/VHDL/evr320/hdl {
+	pkg_v6vlx_gtxe1.vhd \
+	evr320_tmem.vhd \
+	evr320_ifc1210_wrapper.vhd \
+} -tag ifc1210

sim/run.tcl

@@ -0,0 +1,24 @@
+#Load dependencies
+source ../../../TCL/PsiSim/PsiSim.tcl
+
+#Import psi::sim library
+namespace import psi::sim::*
+
+#Initialize Simulation
+init
+
+#Configure
+source ./config.tcl
+
+#Run Simulation
+puts "------------------------------"
+puts "-- Compile EVR320 Core"
+puts "------------------------------"
+compile_files -tag lib -clean
+#puts "------------------------------"
+#puts "-- Compile TOSCA2 Bindings"
+#puts "------------------------------"
+#compile_files -tag tosca2 
+#compile_files -tag ifc1210
+
+run_check_errors "###ERROR###"