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b0607ab3ca
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v1.0.0-rc.34
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2025-04-14 11:52:06 +02:00 |
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ddf4c75645
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v1.0.0-rc.31
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2025-03-02 13:15:28 +01:00 |
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28d224afab
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version 1.0.0-rc.25
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2024-11-22 21:25:20 +01:00 |
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adc13ff33e
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version 1.0.0-rc.24
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2024-11-17 14:55:09 +01:00 |
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1717e171b9
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Modifications after CristallinaMX beamtime
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2024-06-27 20:26:11 +02:00 |
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c6d2b5eedf
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File writer and spot finding improvements
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2024-04-08 11:18:50 +02:00 |
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d315506633
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* Enhancements for XFEL
* Enhancements for EIGER
* Writer is more flexible and capable of handling DECTRIS data
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2024-03-05 20:41:47 +01:00 |
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babb1a5c8d
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Fixes after MAX IV experiment
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2024-02-05 17:18:16 +01:00 |
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f5f86d9ab6
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Modifications in preparation to MAX IV experiment
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2024-01-27 21:23:56 +01:00 |
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d82bd13917
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Minor fixes for CI and dependencies
Improvements in documentation and readability of JungfraujochDevice function
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2023-12-14 22:39:17 +01:00 |
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1798de247b
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Extend FPGA functionality
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2023-12-09 12:08:39 +01:00 |
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1b2b8f5863
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FPGA: Fix problems in summation and related cores
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2023-11-02 20:25:29 +01:00 |
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2ed91c1849
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FPGA: transfer for image and processing results are separate DMA transactions
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2023-10-28 16:47:06 +02:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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a611d3f08b
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FPGA: Adapt host writer to multipixel core. (TODO -> multipixels should be masked for rad. int. and spot finding)
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2023-10-24 19:11:23 +02:00 |
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7008703af3
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FPGA: Integration is not calculating sum2
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2023-10-20 14:06:58 +02:00 |
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736a181e5e
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HLS: Spot finder outputs parameters + statistics
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2023-10-18 15:19:01 +02:00 |
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ca118f26d5
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FPGA: integration results are reduced to cover two bins per 512-bit
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2023-09-29 22:07:52 +02:00 |
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549cc6a887
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FPGA: Add ADU histogram (work in progress; needs test)
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2023-09-29 16:55:37 +02:00 |
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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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0f7c14c267
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FPGA: integration calculates sum^2
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2023-09-25 22:23:06 +02:00 |
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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df0b0d8b96
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FPGA: add spot finder to the design
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2023-09-24 19:04:58 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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21bed7ee72
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FPGA: host_writer writes module statistics
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2023-09-21 13:19:23 +02:00 |
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8c1bc9d89d
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FPGA: Remove non-blocking mode
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2023-09-20 16:41:14 +02:00 |
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25ce039e92
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FPGA: Modifications to host_writer to make it functionally closer to old one
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2023-09-19 21:24:37 +02:00 |
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2982097b8c
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FPGA: Use HBM as intermediary cache for images
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2023-09-19 07:36:56 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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309dabd32b
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FPGA: Use dedicated struct for address exchange
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2023-09-11 11:19:05 +02:00 |
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6cd8d768ea
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FPGA: save_to_hbm uses dedicated data structure for completion
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2023-09-11 10:50:15 +02:00 |
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0421e517fc
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FPGA: host writer - fix wrong req handle check + add marker in work complection for flushing frame
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2023-07-25 12:40:57 +02:00 |
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13b2e16b33
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FPGA: handle better weird work request handle
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2023-07-25 12:40:57 +02:00 |
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35b3704ccf
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FPGA: ignore packets with module number out of bounds + set bit in error register
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2023-07-25 12:40:57 +02:00 |
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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