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FPGA: handle better weird work request handle

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This commit is contained in:
leonarski_f
2023-07-25 12:00:55 +02:00
parent 847ca0922c
commit 13b2e16b33
1 changed files with 6 additions and 3 deletions
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fpga/hls/host_writer.cpp
+6 -3
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@@ -192,7 +192,12 @@ void host_writer(STREAM_512 &data_in,
comp_debug, comp_timestamp, comp_bunchid,
comp_exptime, data_collection_id);
}
if (module_number >= nmodules) {
if (req_handle >= HANDLE_SKIP_FRAME) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[4] = 1;
} else if (module_number >= nmodules) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[5] = 1;
@@ -204,8 +209,6 @@ void host_writer(STREAM_512 &data_in,
internal_err_reg[2] = 1;
}
if (req_handle >= HANDLE_START)
internal_err_reg[4] = 1;
handle[id] = req_handle;
curr_frame[id] = frame_number;