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FPGA: host writer - fix wrong req handle check + add marker in work complection for flushing frame

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This commit is contained in:
leonarski_f
2023-07-25 12:21:32 +02:00
parent 13b2e16b33
commit 0421e517fc
1 changed files with 13 additions and 12 deletions
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25
fpga/hls/host_writer.cpp
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@@ -19,14 +19,15 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
const ap_uint<64> &timestamp,
const ap_uint<64> &bunchid,
const ap_uint<32> &exptime,
const ap_uint<32> &data_collection_id) {
const ap_uint<32> &data_collection_id,
const ap_uint<1> &flushing) {
#pragma HLS INLINE
ap_uint<1> all_packets_ok = packet_mask.and_reduce();
ap_uint<1> any_packets_received = packet_mask.or_reduce();
ap_uint<8> status = 0;
status[0] = all_packets_ok;
status[1] = any_packets_received;
status[2] = flushing;
ap_uint<128> tmp = (handle, packet_count, status, module_number, frame_num);
status[7] = tmp.xor_reduce(); // ensure completion has even parity
@@ -153,7 +154,7 @@ void host_writer(STREAM_512 &data_in,
ap_uint<8> internal_err_reg = 0;
err_reg = internal_err_reg;
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id);
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0);
idle = 0;
uint64_t total_counter = 0;
@@ -190,14 +191,10 @@ void host_writer(STREAM_512 &data_in,
write_completion(m_axis_completion, comp_handle, module_number,
comp_frame, comp_packet_mask, comp_packet_count,
comp_debug, comp_timestamp, comp_bunchid,
comp_exptime, data_collection_id);
comp_exptime, data_collection_id, 0);
}
if (req_handle >= HANDLE_SKIP_FRAME) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[4] = 1;
} else if (module_number >= nmodules) {
if (module_number >= nmodules) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[5] = 1;
@@ -207,9 +204,13 @@ void host_writer(STREAM_512 &data_in,
} else {
if (read_request(s_axis_work_request, req_handle, req_host_offset))
internal_err_reg[2] = 1;
if (req_handle >= HANDLE_SKIP_FRAME) {
req_handle = HANDLE_SKIP_FRAME;
req_host_offset = 0;
internal_err_reg[4] = 1;
}
}
handle[id] = req_handle;
curr_frame[id] = frame_number;
curr_offset[id] = req_host_offset;
@@ -266,11 +267,11 @@ void host_writer(STREAM_512 &data_in,
write_completion(m_axis_completion, handle[m], m / 2, curr_frame[m],
packet_mask[m], packet_count[m],
debug[m], timestamp[m], jf_bunchid[m],
exptime[m], data_collection_id);
exptime[m], data_collection_id, 1);
}
data_in >> packet_in;
write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id);
write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0);
idle = 1;
}