From 0421e517fc2cd7621684c787386de54da7f5c3f9 Mon Sep 17 00:00:00 2001 From: Filip Leonarski Date: Tue, 25 Jul 2023 12:21:32 +0200 Subject: [PATCH] FPGA: host writer - fix wrong req handle check + add marker in work complection for flushing frame --- fpga/hls/host_writer.cpp | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/fpga/hls/host_writer.cpp b/fpga/hls/host_writer.cpp index 4b17134d..8a923327 100644 --- a/fpga/hls/host_writer.cpp +++ b/fpga/hls/host_writer.cpp @@ -19,14 +19,15 @@ inline void write_completion(hls::stream > &m_axis_completion, const ap_uint<64> ×tamp, const ap_uint<64> &bunchid, const ap_uint<32> &exptime, - const ap_uint<32> &data_collection_id) { + const ap_uint<32> &data_collection_id, + const ap_uint<1> &flushing) { #pragma HLS INLINE ap_uint<1> all_packets_ok = packet_mask.and_reduce(); ap_uint<1> any_packets_received = packet_mask.or_reduce(); ap_uint<8> status = 0; status[0] = all_packets_ok; status[1] = any_packets_received; - + status[2] = flushing; ap_uint<128> tmp = (handle, packet_count, status, module_number, frame_num); status[7] = tmp.xor_reduce(); // ensure completion has even parity @@ -153,7 +154,7 @@ void host_writer(STREAM_512 &data_in, ap_uint<8> internal_err_reg = 0; err_reg = internal_err_reg; - write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id); + write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0); idle = 0; uint64_t total_counter = 0; @@ -190,14 +191,10 @@ void host_writer(STREAM_512 &data_in, write_completion(m_axis_completion, comp_handle, module_number, comp_frame, comp_packet_mask, comp_packet_count, comp_debug, comp_timestamp, comp_bunchid, - comp_exptime, data_collection_id); + comp_exptime, data_collection_id, 0); } - if (req_handle >= HANDLE_SKIP_FRAME) { - req_handle = HANDLE_SKIP_FRAME; - req_host_offset = 0; - internal_err_reg[4] = 1; - } else if (module_number >= nmodules) { + if (module_number >= nmodules) { req_handle = HANDLE_SKIP_FRAME; req_host_offset = 0; internal_err_reg[5] = 1; @@ -207,9 +204,13 @@ void host_writer(STREAM_512 &data_in, } else { if (read_request(s_axis_work_request, req_handle, req_host_offset)) internal_err_reg[2] = 1; + if (req_handle >= HANDLE_SKIP_FRAME) { + req_handle = HANDLE_SKIP_FRAME; + req_host_offset = 0; + internal_err_reg[4] = 1; + } } - handle[id] = req_handle; curr_frame[id] = frame_number; curr_offset[id] = req_host_offset; @@ -266,11 +267,11 @@ void host_writer(STREAM_512 &data_in, write_completion(m_axis_completion, handle[m], m / 2, curr_frame[m], packet_mask[m], packet_count[m], debug[m], timestamp[m], jf_bunchid[m], - exptime[m], data_collection_id); + exptime[m], data_collection_id, 1); } data_in >> packet_in; - write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id); + write_completion(m_axis_completion, HANDLE_END, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id, 0); idle = 1; }