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FPGA: Modifications to host_writer to make it functionally closer to old one

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leonarski_f
2023-09-19 21:24:37 +02:00
parent 18a138cd04
commit 25ce039e92
1 changed files with 15 additions and 8 deletions
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23
fpga/hls/host_writer.cpp
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@@ -19,7 +19,7 @@ inline void write_completion(hls::stream<ap_uint<32> > &m_axis_completion,
const ap_uint<64> &timestamp,
const ap_uint<64> &bunchid,
const ap_uint<32> &exptime,
const ap_uint<16> &data_collection_id) {
const ap_uint<32> &data_collection_id) {
#pragma HLS INLINE
ap_uint<1> all_packets_ok = packet_mask.and_reduce();
ap_uint<1> any_packets_received = packet_mask.or_reduce();
@@ -91,26 +91,36 @@ void host_writer(STREAM_512 &data_in,
#pragma HLS INTERFACE register both axis port=datamover_out_cmd
#pragma HLS INTERFACE register both axis port=m_axis_completion
#pragma HLS INTERFACE register both axis port=s_axis_work_request
#pragma HLS INTERFACE register ap_none port=idle
#pragma HLS INTERFACE register ap_vld port=packets_processed
#pragma HLS INTERFACE register ap_vld port=err_reg
#pragma HLS INTERFACE register ap_none port=idle
err_reg = 0;
idle = 1;
ap_uint<32> req_handle;
ap_uint<64> req_host_offset;
while (data_in.empty()) {
#pragma HLS PIPELINE II=4
if (!s_axis_work_request.empty())
read_request(s_axis_work_request, req_handle, req_host_offset);
}
packet_512_t packet;
data_in >> packet;
ap_uint<32> data_collection_mode = ACT_REG_MODE(packet.data);
ap_uint<16> data_collection_id = data_collection_mode(31, 16);
ap_uint<32> data_collection_id = data_collection_mode(31, 16);
ap_uint<1> mode_nonblocking = (data_collection_mode & MODE_NONBLOCKING_ON_WR) ? 1 : 0;
err_reg = 0;
idle = 0;
uint64_t internal_packets_processed = 0;
packets_processed = internal_packets_processed;
write_completion(m_axis_completion, HANDLE_START, 0, 0, 0, 0, 0, 0, 0, 0, data_collection_id);
idle = 0;
axis_completion cmpl;
s_axis_completion >> cmpl;
while (!cmpl.last) {
@@ -118,9 +128,6 @@ void host_writer(STREAM_512 &data_in,
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++)
data_in >> packet;
} else {
ap_uint<32> req_handle;
ap_uint<64> req_host_offset;
read_request(s_axis_work_request, req_handle, req_host_offset);
setup_datamover(datamover_out_cmd, req_host_offset, RAW_MODULE_SIZE * sizeof(uint16_t));
for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / 64; i++) {