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2dfd878d01
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JFConversionFloatingPoint: Integrate other bit depths/signs
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2023-11-07 15:36:49 +01:00 |
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be546e9f76
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JFConversionFloatingPoint: Move to double type (32-bit special values can be only exact in double type)
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2023-11-07 14:31:59 +01:00 |
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de317c29d5
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JFConversion: Clean-up
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2023-11-07 13:28:27 +01:00 |
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310d77a57f
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JFJochReceiver: No access to preview frame via gRPC
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2023-11-07 10:13:19 +01:00 |
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552597523d
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ImagePusher: Serialization of StartMessage is handled outside of the class
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2023-11-06 20:21:27 +01:00 |
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591e724cf6
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DiffractionExperiment: Rename GetFPGAOutputDepth -> GetPixelDepth and GetFPGASummation -> GetSummation
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2023-11-06 18:01:53 +01:00 |
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dec3eb15de
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FrameTransformation: Add two tests for int32 and uint16
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2023-11-06 17:43:14 +01:00 |
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d6c1b19599
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DiffractionExperiment: Remove ROI-mask function
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2023-11-06 16:51:34 +01:00 |
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b2743072e6
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DiffractionExperiment: Remove frame summation (summation only on FPGA)
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2023-11-06 16:09:08 +01:00 |
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fcd7612656
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DiffractionExperiment: Remove 2x2 binning to simplify transformation code
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2023-11-06 14:16:15 +01:00 |
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e6442f6384
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ZMQPreviewPublisher: Support both 16-bit and 32-bit images in preview
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2023-11-03 17:38:23 +01:00 |
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50556932fb
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DiffractionExperiment: Remove spot finder stride
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2023-11-03 16:56:50 +01:00 |
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72045655b4
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JFJochReceiver: Use FPGA based spot finder
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2023-11-03 12:39:12 +01:00 |
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ca4b940904
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StrongPixelSet: ReadFPGAOutput (not tested)
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2023-11-03 12:09:33 +01:00 |
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71960d5496
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JFJochReceiver: Remove MiniSummationThread (as summation is anyway handled on FPGA)
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2023-11-03 11:25:14 +01:00 |
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3d7c7b0779
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Implement FPGA summation
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2023-11-02 20:41:37 +01:00 |
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1b2b8f5863
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FPGA: Fix problems in summation and related cores
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2023-11-02 20:25:29 +01:00 |
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c66c06e8f5
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FPGA: Fix setup action
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2023-11-02 15:09:04 +01:00 |
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8cd0d497ad
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FPGA: Allow saving 32-bit unsigned.
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2023-11-02 13:32:29 +01:00 |
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f21f226a59
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Move MAX_FPGA_SUMMATION to Definitions.h
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2023-11-02 12:55:52 +01:00 |
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b3eceef7cd
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FPGA: Max module number is 32
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2023-11-01 15:55:06 +01:00 |
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9f110f3c1a
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FPGA: nmodules is actually module - 1 (there will be never 0 modules, while it can encode 32)
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2023-11-01 14:28:32 +01:00 |
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112a62fc7f
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FPGA: remove limit of modules for frame_generator
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2023-11-01 14:20:43 +01:00 |
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8f2b01be80
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FPGA: frame_generator and load_calibration return value for error checking
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2023-11-01 13:31:41 +01:00 |
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a71121482e
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FPGAIntegrationTest: More parameters in packet generator custom frame test
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2023-11-01 13:29:06 +01:00 |
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31304553be
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FPGA: sls_detector had hardcoded max module number -> fixed
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2023-11-01 13:28:17 +01:00 |
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3940f067a8
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MAX_MODULES_FPGA moved to Definitions.h => This needs to be const for RELEASE_LEVEL
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2023-11-01 13:16:22 +01:00 |
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b84febed5c
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FPGA: Update max summation to 128
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2023-11-01 12:23:25 +01:00 |
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a17b75862e
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Update CI scripts. Remove retaining .bit files (large and not useful) and remove RHEL7 specific parts.
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2023-11-01 12:18:37 +01:00 |
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e0ef39a9ec
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Update README.md
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2023-11-01 12:18:37 +01:00 |
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f9ac919e3c
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Merge branch 'fpga_multipixel' into 'main'
FPGA: Add capability for auto-summation and image processing to the FPGA
See merge request jungfraujoch/nextgendcu!9
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2023-10-29 11:29:46 +01:00 |
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05a35855eb
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Extend frame summation to 64
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2023-10-28 17:07:22 +02:00 |
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270dd1224b
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Receiver: remove JF conversion on CPU
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2023-10-28 17:00:04 +02:00 |
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c8862c8aa6
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Receiver: remove Mellanox device and Linux socket (both are much less functional as compared to FPGA)
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2023-10-28 16:50:55 +02:00 |
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2ed91c1849
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FPGA: transfer for image and processing results are separate DMA transactions
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2023-10-28 16:47:06 +02:00 |
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961c17c4d0
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FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
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2023-10-28 16:35:33 +02:00 |
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fbc4f79a40
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FPGA: Frame_summation operates internally on 24-bit integers
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2023-10-28 06:22:06 +02:00 |
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4fbd747341
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FPGA: Remove multipixel from the pipeline
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2023-10-27 20:47:44 +02:00 |
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d562a4b435
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FPGA driver: Remove TODO for sysfs from README
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2023-10-27 19:51:59 +02:00 |
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28673ffc63
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Merge branch 'pcie_driver_sysfs' into 'main'
PCIe driver: Added sysfs bindings
See merge request jungfraujoch/nextgendcu!8
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2023-10-27 19:49:47 +02:00 |
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673e0f610a
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FPGA driver: Read MAC address from CMS on card initialization
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2023-10-27 19:48:40 +02:00 |
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4978149fdd
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FPGA: Add register slice in the data pipeline
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2023-10-27 19:43:40 +02:00 |
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c896ec5659
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FPGA: Remove bitshuffle from the pipeline
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2023-10-27 19:41:02 +02:00 |
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f46a8e47a0
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FPGA: Use AggressiveExplore for routing
|
2023-10-27 19:12:27 +02:00 |
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817d541fb0
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HLS: save_to_hbm.cpp send frames in proper order
|
2023-10-27 16:02:23 +02:00 |
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08c2427fc7
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FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign
|
2023-10-27 15:42:24 +02:00 |
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e06086e956
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HLSSimulatedDevice: Change order integration -> frame_summation -> spot finding
|
2023-10-27 15:41:09 +02:00 |
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b08071887b
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HLSSimulatedDevice: Add frame_summation
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2023-10-27 15:36:19 +02:00 |
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700d5b25af
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HLSSimulatedDevice: Add frame_summation_reoder_compl
|
2023-10-27 15:33:29 +02:00 |
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3b802effa8
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HLSSimulatedDevice: Remove module_upside_down
|
2023-10-27 15:28:49 +02:00 |
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