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653 Commits 89 Branches 152 Tags
03d2acfbe27a22ccafcc789660dfd6e2eeff4408
Commit Graph
184 Commits
Author SHA1 Message Date
leonarski_f 050d762187 Remove FPGAStatus - replace it with non-ProtoBuf version 2023-11-08 21:01:36 +01:00
leonarski_f 98cb58d199 PCIe driver: Fix addresses for calibration and frame generator 2023-11-08 14:36:36 +01:00
leonarski_f 427f0f7a45 Fix tests + re-run FPGA synthesis 2023-11-07 21:42:16 +01:00
leonarski_f adc0a1bab6 Fix tests + re-run FPGA synthesis 2023-11-07 21:36:22 +01:00
leonarski_f 41985b6c29 FPGA: Increase data width of conversion to 18-bit. This allows to use full unsigned precision + raw data are handled properly. 2023-11-07 19:11:37 +01:00
leonarski_f 1b2b8f5863 FPGA: Fix problems in summation and related cores 2023-11-02 20:25:29 +01:00
leonarski_f c66c06e8f5 FPGA: Fix setup action 2023-11-02 15:09:04 +01:00
leonarski_f 8cd0d497ad FPGA: Allow saving 32-bit unsigned. 2023-11-02 13:32:29 +01:00
leonarski_f f21f226a59 Move MAX_FPGA_SUMMATION to Definitions.h 2023-11-02 12:55:52 +01:00
leonarski_f b3eceef7cd FPGA: Max module number is 32 2023-11-01 15:55:06 +01:00
leonarski_f 9f110f3c1a FPGA: nmodules is actually module - 1 (there will be never 0 modules, while it can encode 32) 2023-11-01 14:28:32 +01:00
leonarski_f 112a62fc7f FPGA: remove limit of modules for frame_generator 2023-11-01 14:20:43 +01:00
leonarski_f 8f2b01be80 FPGA: frame_generator and load_calibration return value for error checking 2023-11-01 13:31:41 +01:00
leonarski_f 31304553be FPGA: sls_detector had hardcoded max module number -> fixed 2023-11-01 13:28:17 +01:00
leonarski_f 3940f067a8 MAX_MODULES_FPGA moved to Definitions.h => This needs to be const for RELEASE_LEVEL 2023-11-01 13:16:22 +01:00
leonarski_f b84febed5c FPGA: Update max summation to 128 2023-11-01 12:23:25 +01:00
leonarski_f e0ef39a9ec Update README.md 2023-11-01 12:18:37 +01:00
leonarski_f f9ac919e3c Merge branch 'fpga_multipixel' into 'main' 
FPGA: Add capability for auto-summation and image processing to the FPGA

See merge request jungfraujoch/nextgendcu!9
 2023-10-29 11:29:46 +01:00
leonarski_f 05a35855eb Extend frame summation to 64 2023-10-28 17:07:22 +02:00
leonarski_f 2ed91c1849 FPGA: transfer for image and processing results are separate DMA transactions 2023-10-28 16:47:06 +02:00
leonarski_f 961c17c4d0 FPGA: data analysis is done based on 24-bit numbers - allowing frame summation 2023-10-28 16:35:33 +02:00
leonarski_f fbc4f79a40 FPGA: Frame_summation operates internally on 24-bit integers 2023-10-28 06:22:06 +02:00
leonarski_f 4fbd747341 FPGA: Remove multipixel from the pipeline 2023-10-27 20:47:44 +02:00
leonarski_f d562a4b435 FPGA driver: Remove TODO for sysfs from README 2023-10-27 19:51:59 +02:00
leonarski_f 28673ffc63 Merge branch 'pcie_driver_sysfs' into 'main' 
PCIe driver: Added sysfs bindings

See merge request jungfraujoch/nextgendcu!8
 2023-10-27 19:49:47 +02:00
leonarski_f 673e0f610a FPGA driver: Read MAC address from CMS on card initialization 2023-10-27 19:48:40 +02:00
leonarski_f 4978149fdd FPGA: Add register slice in the data pipeline 2023-10-27 19:43:40 +02:00
leonarski_f c896ec5659 FPGA: Remove bitshuffle from the pipeline 2023-10-27 19:41:02 +02:00
leonarski_f f46a8e47a0 FPGA: Use AggressiveExplore for routing 2023-10-27 19:12:27 +02:00
leonarski_f 817d541fb0 HLS: save_to_hbm.cpp send frames in proper order 2023-10-27 16:02:23 +02:00
leonarski_f 08c2427fc7 FPGA: Refactor FPGA (add two hierarchy groups for jungfraujoch) + change order similar to HLSSimulatedDesign 2023-10-27 15:42:24 +02:00
leonarski_f 7973c2ca81 HLS: Minor fixes to adu_histo.cpp 2023-10-27 15:27:36 +02:00
leonarski_f 4fbac629d6 HLS: Use U55C part number for proper usage statistics 2023-10-27 13:54:35 +02:00
leonarski_f b022dd0055 Improved FPGA README.md 2023-10-27 12:24:50 +02:00
leonarski_f cf69aef472 FPGA: Add extra register slices for upside_down 2023-10-26 22:36:08 +02:00
leonarski_f 2268486824 HLS: Added frame_summation core 2023-10-26 22:31:09 +02:00
leonarski_f 4011c4541d HLS: frames inside HLS logic are counted from 0, even if JUNGFRAU counts them from 1 2023-10-26 19:42:15 +02:00
leonarski_f 473bf17ae7 HLS: axis_completion has extra parameter (ignore) that makes the frame ignored by load_from_hbm, but HBM handle is still recovered 2023-10-26 18:14:35 +02:00
leonarski_f 4e60bb2f9e FPGA: Add option to invert modules upside down 2023-10-25 22:20:45 +02:00
leonarski_f 439d6fa12a FPGA: Spot finder won't use multipixels for mean/variance calculation 2023-10-25 18:18:29 +02:00
leonarski_f 6bcf54f603 FPGA: Add bitshuffle to the design (warning! no test for full integration!) 2023-10-25 11:07:21 +02:00
leonarski_f a611d3f08b FPGA: Adapt host writer to multipixel core. (TODO -> multipixels should be masked for rad. int. and spot finding) 2023-10-24 19:11:23 +02:00
leonarski_f d408b3ed2a FPGA: Integrate add multipixel into the design 2023-10-24 18:58:59 +02:00
leonarski_f c37a9fa768 FPGA: Add multipixel - handle division by 2 and 4 for multipixels. 2023-10-24 18:05:48 +02:00
leonarski_f e1a6830c50 FPGA: Add multipixel (-> TODO calculate proper number) 2023-10-24 16:43:24 +02:00
leonarski_f 79d7254555 PCIe driver: Added sysfs bindings 2023-10-24 09:25:43 +02:00
leonarski_f 19644a1f5f FPGA: Trigger synthesis 2023-10-21 16:12:51 +02:00
leonarski_f 4ede0f1f15 FPGA: rename axis_256_to_512.cpp file 2023-10-21 15:38:40 +02:00
leonarski_f 3b65e6bf88 FPGA: Integration on FPGA allows for per pixel weights (in range 1.99 - 3e-5) 2023-10-21 15:37:46 +02:00
leonarski_f 7008703af3 FPGA: Integration is not calculating sum2 2023-10-20 14:06:58 +02:00