1ab257af6c
v1.0.0-rc.125 ( #32 )
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This is an UNSTABLE release. This version adds scalign and merging. These are experimental at the moment, and should not be used for production analysis.
If things go wrong with analysis, it is better to revert to 1.0.0-rc.124.
* jfjoch_broker: Improve logic on switching on/off spot finding
* jfjoch_broker: Increase maximum spot count for FFBIDX to 65536
* jfjoch_broker: Increase default maximum unit cell for FFT to 500 A (could have performance impact, TBD)
* jfjoch_process: Add scalign and merging functionality - program is experimental at the moment and should not be used for production analysis
* jfjoch_viewer: Display partiality and reciprocal Lorentz-polarization correction for each reflection
* jfjoch_writer: Save more information about each reflection
Reviewed-on: #32
Co-authored-by: Filip Leonarski <filip.leonarski@psi.ch >
Co-committed-by: Filip Leonarski <filip.leonarski@psi.ch >
2026-02-18 16:17:21 +01:00
5d9d2de4a4
v1.0.0-rc.81
2025-09-21 19:27:51 +02:00
bb32f27635
v1.0.0-rc.70
2025-08-27 06:21:10 +02:00
20973792e4
v1.0.0-rc.68
2025-08-16 19:59:27 +02:00
ddf4c75645
v1.0.0-rc.31
2025-03-02 13:15:28 +01:00
7564619574
version 1.0.0-rc.29
2024-12-08 13:26:13 +01:00
28d224afab
version 1.0.0-rc.25
2024-11-22 21:25:20 +01:00
adc13ff33e
version 1.0.0-rc.24
2024-11-17 14:55:09 +01:00
ce19996874
version 1.0.0-rc.17
2024-10-14 15:03:38 +02:00
3be959f272
version 1.0.0-rc.14
2024-10-07 11:56:40 +02:00
e812918e2e
version 1.0.0-rc.13
2024-10-05 13:14:49 +02:00
a32c7274a6
Release 1.0.0_rc.9
2024-06-20 11:26:40 +02:00
5312f3ea6a
Improvements in building Jungfraujoch
2024-05-06 21:28:55 +02:00
4e8c3a88a7
Indexing improvements
2024-04-20 13:41:41 +02:00
30599e2858
Fix bug in detector initialize
2024-03-23 04:07:12 +01:00
f5f86d9ab6
Modifications in preparation to MAX IV experiment
2024-01-27 21:23:56 +01:00
d82bd13917
Minor fixes for CI and dependencies
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Improvements in documentation and readability of JungfraujochDevice function
2023-12-14 22:39:17 +01:00
0b69dfb290
New REST+OpenAPI interface
2023-12-11 12:11:54 +01:00
1798de247b
Extend FPGA functionality
2023-12-09 12:08:39 +01:00
d2f1c569a7
FPGA: Modify FPGA register map (move action configuration to offset 0x200)
2023-11-21 15:24:55 +01:00
8635724ca3
Move FPGA register map from Definitions.h to jfjoch_drv.h
2023-11-21 15:20:12 +01:00
1e6f64b4da
FPGA: Increase max summation to 256
2023-11-16 21:32:37 +01:00
98cb58d199
PCIe driver: Fix addresses for calibration and frame generator
2023-11-08 14:36:36 +01:00
f21f226a59
Move MAX_FPGA_SUMMATION to Definitions.h
2023-11-02 12:55:52 +01:00
b3eceef7cd
FPGA: Max module number is 32
2023-11-01 15:55:06 +01:00
112a62fc7f
FPGA: remove limit of modules for frame_generator
2023-11-01 14:20:43 +01:00
3940f067a8
MAX_MODULES_FPGA moved to Definitions.h => This needs to be const for RELEASE_LEVEL
2023-11-01 13:16:22 +01:00
961c17c4d0
FPGA: data analysis is done based on 24-bit numbers - allowing frame summation
2023-10-28 16:35:33 +02:00
2268486824
HLS: Added frame_summation core
2023-10-26 22:31:09 +02:00
4e60bb2f9e
FPGA: Add option to invert modules upside down
2023-10-25 22:20:45 +02:00
e1a6830c50
FPGA: Add multipixel (-> TODO calculate proper number)
2023-10-24 16:43:24 +02:00
4e4a232a6d
Definitions: Increase max gRPC message size to 2 GB -> need to change later how calibration is being transferred
2023-10-20 11:40:09 +02:00
6691b01265
PCIe driver: accept spot finding parameters
2023-10-18 21:23:41 +02:00
98fe70315b
FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design)
2023-09-30 11:28:01 +02:00
549cc6a887
FPGA: Add ADU histogram (work in progress; needs test)
2023-09-29 16:55:37 +02:00
79aef71ce3
FPGA: spot_finder added
2023-09-26 18:54:31 +02:00
84bf69b8a6
FPGA: frame generator reads from HBM (work in progress)
2023-09-26 13:14:43 +02:00
f4f4b50be7
FPGA: frame_generator has 8 module specific frames
2023-09-24 15:43:04 +02:00
f06e92fd1b
FPGA: load_calibration allows to upload integration map
2023-09-22 18:28:35 +02:00
2c9d623265
integration: use separate FIFO for integration results
2023-09-22 17:49:14 +02:00
2eb85496f2
FPGA: add integration routine (work in progress)
2023-09-21 17:12:01 +02:00
a5aed37100
Definitions.h: Increase space for data processing results
2023-09-21 10:08:53 +02:00
8c1bc9d89d
FPGA: Remove non-blocking mode
2023-09-20 16:41:14 +02:00
7396ee342c
FPGA: Increase release level to make sure FPGA is using 1 MiB bursts only
2023-09-19 13:13:23 +02:00
16bbf54f2a
Remove open source license (for now)
2023-09-15 10:47:21 +02:00
0b95456d3d
Adapt PCIe driver and tests for the new frame generator
2023-09-13 21:44:20 +02:00
7a635f1ee8
FPGA: load_calibration clean-up + simplification
2023-09-12 09:16:45 +02:00
6251c58f32
FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
2023-09-08 19:08:37 +02:00
3aeb3e09ee
FPGA: Do not load internal packet generator frame via DMA
2023-09-06 11:57:16 +02:00
2f7b46290a
FPGA: Enable non-power of 2 storage cell number
2023-07-04 21:59:48 +02:00
