93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
// Copyright (2019-2023) Paul Scherrer Institute
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#ifndef DEFINITIONS_H
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#define DEFINITIONS_H
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#define WVL_1A_IN_KEV 12.39854f
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#define DELAY_FRAMES_STOP_AND_QUIT 5
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#define RAW_MODULE_LINES (512L)
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#define RAW_MODULE_COLS (1024L)
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#define RAW_MODULE_SIZE (RAW_MODULE_LINES * RAW_MODULE_COLS)
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#define CONVERTED_MODULE_LINES (514L)
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#define CONVERTED_MODULE_COLS (1030L)
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#define CONVERTED_MODULE_SIZE (CONVERTED_MODULE_LINES * CONVERTED_MODULE_COLS)
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#define JUNGFRAU_PACKET_SIZE_BYTES (8192)
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#define FPGA_BUFFER_LOCATION_SIZE (RAW_MODULE_SIZE * sizeof(short) * 4) // account for space for data processing results and 32-bit frames
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#define MIN_COUNT_TIME_IN_US 5
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#define MIN_FRAME_TIME_HALF_SPEED_IN_US 1000
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#define MIN_FRAME_TIME_FULL_SPEED_IN_US 470
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#define MAX_FRAME_TIME 2000
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#define MIN_STORAGE_CELL_DELAY_IN_NS 2100
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#define READOUT_TIME_IN_US 20
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#define GRPC_MAX_MESSAGE_SIZE (2*1000L*1000L*1000L)
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#define MIN_ENERGY 0.1
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#define MAX_ENERGY 25.0
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#define PEDESTAL_WINDOW_SIZE 128
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#define PEDESTAL_WRONG 16384
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#define FRAME_TIME_PEDE_G1G2_IN_US (10*1000)
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#define SENSOR_THICKNESS_IN_UM 320.0
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#define PIXEL_SIZE_IN_UM 75.0
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#define PIXEL_SIZE_IN_MM (PIXEL_SIZE_IN_UM/1000.0)
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#define SENSOR_MATERIAL "Si"
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#define GAIN_G0_MULTIPLIER 32
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#define GAIN_G1_MULTIPLIER (-1)
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#define GAIN_G2_MULTIPLIER (-1)
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#define DEFAULT_G0_FACTOR (41.0)
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#define DEFAULT_G1_FACTOR (-1.439)
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#define DEFAULT_G2_FACTOR (-0.1145)
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// For FPGA
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#define ACTION_TYPE 0x52324158
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#define RELEASE_LEVEL 0x0046
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#define MODE_CONV 0x0001L
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#define MODE_BITSHUFFLE_FPGA 0x0002L
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#define MODE_ADD_MULTIPIXEL 0x0004L
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#define MODE_MODULE_UPSIDE_DOWN 0x0008L
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#define MODE_32BIT 0x0010L
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#define MODE_UNSIGNED 0x0020L
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#define TASK_NO_DATA_STREAM UINT16_MAX
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#define PIXEL_OUT_SATURATION (INT16_MAX)
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#define PIXEL_OUT_LOST (INT16_MIN)
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#define PIXEL_OUT_0xFFFF (INT16_MIN)
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#define PIXEL_OUT_G1_SATURATION (INT16_MIN)
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#define PIXEL_OUT_GAINBIT_2 (INT16_MIN)
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#define LOAD_CALIBRATION_BRAM_SIZE 1632
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#define LOAD_CALIBRATION_DEST_CALIB 0
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#define LOAD_CALIBRATION_DEST_INTEGRATION 1
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#define LOAD_CALIBRATION_DEST_FRAME_GEN 2
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// FPGA register map
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#define HANDLE_START (UINT32_MAX - 1)
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#define HANDLE_SKIP_FRAME (UINT32_MAX - 2)
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#define HANDLE_END (UINT32_MAX )
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#define INT_PKT_GEN_DEBUG 0x0
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#define INT_PKT_GEN_BUNCHID 0xCACACACACA
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#define INT_PKT_GEN_EXPTTIME 10000
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#define FPGA_INTEGRATION_BIN_COUNT 1024
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#define MAX_MODULES_FPGA 32
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#define MAX_FPGA_SUMMATION 256
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#define ADU_HISTO_BIN_WIDTH 32
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#define ADU_HISTO_BIN_COUNT (65536/ ADU_HISTO_BIN_WIDTH)
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#endif //DEFINITIONS_H
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