FPGA: Modify FPGA register map (move action configuration to offset 0x200)
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@@ -48,7 +48,7 @@
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// For FPGA
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#define ACTION_TYPE 0x52324158
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#define RELEASE_LEVEL 0x0045
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#define RELEASE_LEVEL 0x0046
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#define MODE_CONV 0x0001L
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#define MODE_BITSHUFFLE_FPGA 0x0002L
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@@ -141,17 +141,18 @@ FPGA setup can be done via 32-bit registers:
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| 0x010058 | 64 | Valid UDP packets | R | cleared on reset |
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| 0x010060 | 64 | Valid detector packets processed by the card | R | cleared on reset |
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| 0x010066 | 64 | Packets flagged as errors by CMAC | R | cleared on reset |
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| 0x010080 | 64 | MAC address of FPGA card | R/W | network byte order |
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| 0x010088 | 32 | IPv4 address of FPGA card | R/W | network byte order |
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| 0x01008C | 32 | Number of detector modules | R/W | |
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| 0x010090 | 32 | Data collection mode | R/W | |
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| | | Bit 0 - Conversion to photons | | |
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| | | Bit 16:31 - Data collection ID (carried with completions) | | |
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| 0x010094 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | |
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| 0x010098 | 32 | Number of frames expected in the data collection (defines termination condition) | R/W | |
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| 0x01009C | 32 | Number of storage cells | R/W | |
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| 0x010100 | 32 | Spot finder photon count threshold | R/W | |
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| 0x010104 | 32 | Spot finder signal-to-noise ratio threshold (in fixed-point: 6 int. + 4 frac. bit format) | R/W | |
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| 0x010200 | 64 | MAC address of FPGA card | R/W | network byte order |
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| 0x010208 | 32 | IPv4 address of FPGA card | R/W | network byte order |
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| 0x01020C | 32 | Number of detector modules | R/W | |
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| 0x010210 | 32 | Data collection mode | R/W | |
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| | | Bit 0 - Conversion to photons | | |
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| | | Bit 16:31 - Data collection ID (carried with completions) | | |
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| 0x010214 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | |
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| 0x010218 | 32 | Number of frames expected in the data collection (defines termination condition) | R/W | |
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| 0x01021C | 32 | Number of storage cells | R/W | |
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| 0x010220 | 32 | Summation on card (minus one: 0 => summation of 1, 1 => summation of 2, etc.) | R/W | |
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| 0x020000 - 0x02FFFF | | CMAC 100G | | See Xilinx PG203 for register map |
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| 0x030000 - 0x03FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map |
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| 0x040000 - 0x04FFFF | | QuadSPI flash | | See Xilinx PG153 for register map |
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@@ -38,20 +38,20 @@
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`define ADDR_PACKETS_ERR_LEN 16'h0068
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`define ADDR_PACKETS_ERR_ETH 16'h006C
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`define ADDR_MAC_ADDR_LO 16'h0080
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`define ADDR_MAC_ADDR_HI 16'h0084
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`define ADDR_IPV4_ADDR 16'h0088
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`define ADDR_NMODULES 16'h008C
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`define ADDR_DATA_COL_MODE 16'h0090
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`define ADDR_ONE_OVER_ENERGY 16'h0094
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`define ADDR_NFRAMES 16'h0098
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`define ADDR_NSTORAGE_CELLS 16'h009C
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`define ADDR_NSUMMATION 16'h00A0
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`define ADDR_SPOT_FINDER_CNT_THR 16'h0100
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`define ADDR_SPOT_FINDER_SNR_THR 16'h0104
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`define ADDR_MAC_ADDR_LO 16'h0200
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`define ADDR_MAC_ADDR_HI 16'h0204
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`define ADDR_IPV4_ADDR 16'h0208
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`define ADDR_NMODULES 16'h020C
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`define ADDR_DATA_COL_MODE 16'h0210
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`define ADDR_ONE_OVER_ENERGY 16'h0214
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`define ADDR_NFRAMES 16'h0218
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`define ADDR_NSTORAGE_CELLS 16'h021C
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`define ADDR_NSUMMATION 16'h0220
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module action_config
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#(parameter C_S_AXI_ADDR_WIDTH = 16,
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@@ -43,7 +43,7 @@
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#define PCIE_OFFSET (0x090000)
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#define FRAME_GEN_OFFSET (0x080000)
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// Action config
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#define ADDR_CTRL_REGISTER 0x0000
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#define ADDR_GIT_SHA1 0x000C
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#define ADDR_ACTION_TYPE 0x0010
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@@ -70,14 +70,14 @@
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#define ADDR_PACKETS_ERR_LEN 0x0068
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#define ADDR_PACKETS_ERR_ETH 0x006C
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#define ADDR_MAC_ADDR_LO 0x0080
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#define ADDR_MAC_ADDR_HI 0x0084
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#define ADDR_IPV4_ADDR 0x0088
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#define ADDR_NMODULES 0x008C
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#define ADDR_DATA_COL_MODE 0x0090
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#define ADDR_ONE_OVER_ENERGY 0x0094
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#define ADDR_NFRAMES 0x0098
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#define ADDR_NSTORAGE_CELLS 0x009C
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#define ADDR_MAC_ADDR_LO 0x0200
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#define ADDR_MAC_ADDR_HI 0x0204
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#define ADDR_IPV4_ADDR 0x0208
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#define ADDR_NMODULES 0x020C
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#define ADDR_DATA_COL_MODE 0x0210
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#define ADDR_ONE_OVER_ENERGY 0x0214
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#define ADDR_NFRAMES 0x0218
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#define ADDR_NSTORAGE_CELLS 0x021C
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#define ADDR_SPOT_FINDER_THRESHOLD 0x0100
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#define ADDR_SPOT_FINDER_SNR 0x0104
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